Skip to content

Commit dc6e4e9

Browse files
zhaoqi5zhaoqi5
authored
[LoongArch][NFC] Pre-commit tests for xvinsve0.{w/d} (#160829)
1 parent 6ffacae commit dc6e4e9

File tree

1 file changed

+353
-0
lines changed

1 file changed

+353
-0
lines changed

‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvinsve0.ll‎

Lines changed: 353 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,353 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
3+
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
4+
5+
;; xvinsve0.w
6+
define void @xvinsve0_v8i32_l_0(ptr %d, ptr %a, ptr %b) nounwind {
7+
; CHECK-LABEL: xvinsve0_v8i32_l_0:
8+
; CHECK: # %bb.0: # %entry
9+
; CHECK-NEXT: xvld $xr0, $a1, 0
10+
; CHECK-NEXT: xvld $xr1, $a2, 0
11+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI0_0)
12+
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI0_0)
13+
; CHECK-NEXT: xvshuf.w $xr2, $xr1, $xr0
14+
; CHECK-NEXT: xvst $xr2, $a0, 0
15+
; CHECK-NEXT: ret
16+
entry:
17+
%va = load <8 x i32>, ptr %a
18+
%vb = load <8 x i32>, ptr %b
19+
%vc = shufflevector <8 x i32> %va, <8 x i32> %vb, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
20+
store <8 x i32> %vc, ptr %d
21+
ret void
22+
}
23+
24+
define void @xvinsve0_v8i32_l_4(ptr %d, ptr %a, ptr %b) nounwind {
25+
; LA32-LABEL: xvinsve0_v8i32_l_4:
26+
; LA32: # %bb.0: # %entry
27+
; LA32-NEXT: ld.w $a2, $a2, 0
28+
; LA32-NEXT: xvld $xr0, $a1, 0
29+
; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 0
30+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 5
31+
; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 1
32+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 6
33+
; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 2
34+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 7
35+
; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 3
36+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 0
37+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 0
38+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 1
39+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 1
40+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 2
41+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 2
42+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 3
43+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 3
44+
; LA32-NEXT: xvpermi.q $xr2, $xr1, 2
45+
; LA32-NEXT: xvst $xr2, $a0, 0
46+
; LA32-NEXT: ret
47+
;
48+
; LA64-LABEL: xvinsve0_v8i32_l_4:
49+
; LA64: # %bb.0: # %entry
50+
; LA64-NEXT: xvld $xr0, $a2, 0
51+
; LA64-NEXT: xvld $xr1, $a1, 0
52+
; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 0
53+
; LA64-NEXT: vinsgr2vr.w $vr0, $a1, 0
54+
; LA64-NEXT: xvpickve2gr.w $a1, $xr1, 5
55+
; LA64-NEXT: vinsgr2vr.w $vr0, $a1, 1
56+
; LA64-NEXT: xvpickve2gr.w $a1, $xr1, 6
57+
; LA64-NEXT: vinsgr2vr.w $vr0, $a1, 2
58+
; LA64-NEXT: xvpickve2gr.w $a1, $xr1, 7
59+
; LA64-NEXT: vinsgr2vr.w $vr0, $a1, 3
60+
; LA64-NEXT: xvpickve2gr.w $a1, $xr1, 0
61+
; LA64-NEXT: vinsgr2vr.w $vr2, $a1, 0
62+
; LA64-NEXT: xvpickve2gr.w $a1, $xr1, 1
63+
; LA64-NEXT: vinsgr2vr.w $vr2, $a1, 1
64+
; LA64-NEXT: xvpickve2gr.w $a1, $xr1, 2
65+
; LA64-NEXT: vinsgr2vr.w $vr2, $a1, 2
66+
; LA64-NEXT: xvpickve2gr.w $a1, $xr1, 3
67+
; LA64-NEXT: vinsgr2vr.w $vr2, $a1, 3
68+
; LA64-NEXT: xvpermi.q $xr2, $xr0, 2
69+
; LA64-NEXT: xvst $xr2, $a0, 0
70+
; LA64-NEXT: ret
71+
entry:
72+
%va = load <8 x i32>, ptr %a
73+
%vb = load <8 x i32>, ptr %b
74+
%vc = shufflevector <8 x i32> %va, <8 x i32> %vb, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 7>
75+
store <8 x i32> %vc, ptr %d
76+
ret void
77+
}
78+
79+
define void @xvinsve0_v8f32_l(ptr %d, ptr %a, ptr %b) nounwind {
80+
; CHECK-LABEL: xvinsve0_v8f32_l:
81+
; CHECK: # %bb.0: # %entry
82+
; CHECK-NEXT: xvld $xr0, $a1, 0
83+
; CHECK-NEXT: xvld $xr1, $a2, 0
84+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI2_0)
85+
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI2_0)
86+
; CHECK-NEXT: xvshuf.w $xr2, $xr1, $xr0
87+
; CHECK-NEXT: xvst $xr2, $a0, 0
88+
; CHECK-NEXT: ret
89+
entry:
90+
%va = load <8 x float>, ptr %a
91+
%vb = load <8 x float>, ptr %b
92+
%vc = shufflevector <8 x float> %va, <8 x float> %vb, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
93+
store <8 x float> %vc, ptr %d
94+
ret void
95+
}
96+
97+
define void @xvinsve0_v8i32_h_1(ptr %d, ptr %a, ptr %b) nounwind {
98+
; CHECK-LABEL: xvinsve0_v8i32_h_1:
99+
; CHECK: # %bb.0: # %entry
100+
; CHECK-NEXT: xvld $xr0, $a1, 0
101+
; CHECK-NEXT: xvld $xr1, $a2, 0
102+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
103+
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI3_0)
104+
; CHECK-NEXT: xvshuf.w $xr2, $xr1, $xr0
105+
; CHECK-NEXT: xvst $xr2, $a0, 0
106+
; CHECK-NEXT: ret
107+
entry:
108+
%va = load <8 x i32>, ptr %a
109+
%vb = load <8 x i32>, ptr %b
110+
%vc = shufflevector <8 x i32> %va, <8 x i32> %vb, <8 x i32> <i32 8, i32 0, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
111+
store <8 x i32> %vc, ptr %d
112+
ret void
113+
}
114+
115+
define void @xvinsve0_v8i32_h_6(ptr %d, ptr %a, ptr %b) nounwind {
116+
; LA32-LABEL: xvinsve0_v8i32_h_6:
117+
; LA32: # %bb.0: # %entry
118+
; LA32-NEXT: xvld $xr0, $a2, 0
119+
; LA32-NEXT: xvpickve2gr.w $a2, $xr0, 4
120+
; LA32-NEXT: ld.w $a1, $a1, 0
121+
; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 0
122+
; LA32-NEXT: xvpickve2gr.w $a2, $xr0, 5
123+
; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 1
124+
; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 2
125+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 7
126+
; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 3
127+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 0
128+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 0
129+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 1
130+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 1
131+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 2
132+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 2
133+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 3
134+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 3
135+
; LA32-NEXT: xvpermi.q $xr2, $xr1, 2
136+
; LA32-NEXT: xvst $xr2, $a0, 0
137+
; LA32-NEXT: ret
138+
;
139+
; LA64-LABEL: xvinsve0_v8i32_h_6:
140+
; LA64: # %bb.0: # %entry
141+
; LA64-NEXT: xvld $xr0, $a2, 0
142+
; LA64-NEXT: xvld $xr1, $a1, 0
143+
; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 4
144+
; LA64-NEXT: vinsgr2vr.w $vr2, $a1, 0
145+
; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 5
146+
; LA64-NEXT: vinsgr2vr.w $vr2, $a1, 1
147+
; LA64-NEXT: xvpickve2gr.w $a1, $xr1, 0
148+
; LA64-NEXT: vinsgr2vr.w $vr2, $a1, 2
149+
; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 7
150+
; LA64-NEXT: vinsgr2vr.w $vr2, $a1, 3
151+
; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 0
152+
; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 0
153+
; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 1
154+
; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 1
155+
; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 2
156+
; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 2
157+
; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 3
158+
; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 3
159+
; LA64-NEXT: xvpermi.q $xr1, $xr2, 2
160+
; LA64-NEXT: xvst $xr1, $a0, 0
161+
; LA64-NEXT: ret
162+
entry:
163+
%va = load <8 x i32>, ptr %a
164+
%vb = load <8 x i32>, ptr %b
165+
%vc = shufflevector <8 x i32> %va, <8 x i32> %vb, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 0, i32 15>
166+
store <8 x i32> %vc, ptr %d
167+
ret void
168+
}
169+
170+
define void @xvinsve0_v8f32_h(ptr %d, ptr %a, ptr %b) nounwind {
171+
; CHECK-LABEL: xvinsve0_v8f32_h:
172+
; CHECK: # %bb.0: # %entry
173+
; CHECK-NEXT: xvld $xr0, $a1, 0
174+
; CHECK-NEXT: xvld $xr1, $a2, 0
175+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI5_0)
176+
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI5_0)
177+
; CHECK-NEXT: xvshuf.w $xr2, $xr1, $xr0
178+
; CHECK-NEXT: xvst $xr2, $a0, 0
179+
; CHECK-NEXT: ret
180+
entry:
181+
%va = load <8 x float>, ptr %a
182+
%vb = load <8 x float>, ptr %b
183+
%vc = shufflevector <8 x float> %va, <8 x float> %vb, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
184+
store <8 x float> %vc, ptr %d
185+
ret void
186+
}
187+
188+
;; xvinsve0.d
189+
define void @xvinsve0_v4i64_l_1(ptr %d, ptr %a, ptr %b) nounwind {
190+
; CHECK-LABEL: xvinsve0_v4i64_l_1:
191+
; CHECK: # %bb.0: # %entry
192+
; CHECK-NEXT: xvld $xr0, $a1, 0
193+
; CHECK-NEXT: xvld $xr1, $a2, 0
194+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI6_0)
195+
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI6_0)
196+
; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0
197+
; CHECK-NEXT: xvst $xr2, $a0, 0
198+
; CHECK-NEXT: ret
199+
entry:
200+
%va = load <4 x i64>, ptr %a
201+
%vb = load <4 x i64>, ptr %b
202+
%vc = shufflevector <4 x i64> %va, <4 x i64> %vb, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
203+
store <4 x i64> %vc, ptr %d
204+
ret void
205+
}
206+
207+
define void @xvinsve0_v4i64_l_2(ptr %d, ptr %a, ptr %b) nounwind {
208+
; LA32-LABEL: xvinsve0_v4i64_l_2:
209+
; LA32: # %bb.0: # %entry
210+
; LA32-NEXT: xvld $xr0, $a2, 0
211+
; LA32-NEXT: xvpickve2gr.w $a2, $xr0, 0
212+
; LA32-NEXT: xvld $xr1, $a1, 0
213+
; LA32-NEXT: vinsgr2vr.w $vr2, $a2, 0
214+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 1
215+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 1
216+
; LA32-NEXT: xvpickve2gr.w $a1, $xr1, 6
217+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 2
218+
; LA32-NEXT: xvpickve2gr.w $a1, $xr1, 7
219+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 3
220+
; LA32-NEXT: xvpickve2gr.w $a1, $xr1, 0
221+
; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
222+
; LA32-NEXT: xvpickve2gr.w $a1, $xr1, 1
223+
; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
224+
; LA32-NEXT: xvpickve2gr.w $a1, $xr1, 2
225+
; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2
226+
; LA32-NEXT: xvpickve2gr.w $a1, $xr1, 3
227+
; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 3
228+
; LA32-NEXT: xvpermi.q $xr0, $xr2, 2
229+
; LA32-NEXT: xvst $xr0, $a0, 0
230+
; LA32-NEXT: ret
231+
;
232+
; LA64-LABEL: xvinsve0_v4i64_l_2:
233+
; LA64: # %bb.0: # %entry
234+
; LA64-NEXT: ld.d $a2, $a2, 0
235+
; LA64-NEXT: xvld $xr0, $a1, 0
236+
; LA64-NEXT: vinsgr2vr.d $vr1, $a2, 0
237+
; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 3
238+
; LA64-NEXT: vinsgr2vr.d $vr1, $a1, 1
239+
; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 0
240+
; LA64-NEXT: vinsgr2vr.d $vr2, $a1, 0
241+
; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 1
242+
; LA64-NEXT: vinsgr2vr.d $vr2, $a1, 1
243+
; LA64-NEXT: xvpermi.q $xr2, $xr1, 2
244+
; LA64-NEXT: xvst $xr2, $a0, 0
245+
; LA64-NEXT: ret
246+
entry:
247+
%va = load <4 x i64>, ptr %a
248+
%vb = load <4 x i64>, ptr %b
249+
%vc = shufflevector <4 x i64> %va, <4 x i64> %vb, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
250+
store <4 x i64> %vc, ptr %d
251+
ret void
252+
}
253+
254+
define void @xvinsve0_v4f64_l(ptr %d, ptr %a, ptr %b) nounwind {
255+
; CHECK-LABEL: xvinsve0_v4f64_l:
256+
; CHECK: # %bb.0: # %entry
257+
; CHECK-NEXT: xvld $xr0, $a1, 0
258+
; CHECK-NEXT: xvld $xr1, $a2, 0
259+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI8_0)
260+
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI8_0)
261+
; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0
262+
; CHECK-NEXT: xvst $xr2, $a0, 0
263+
; CHECK-NEXT: ret
264+
entry:
265+
%va = load <4 x double>, ptr %a
266+
%vb = load <4 x double>, ptr %b
267+
%vc = shufflevector <4 x double> %va, <4 x double> %vb, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
268+
store <4 x double> %vc, ptr %d
269+
ret void
270+
}
271+
272+
define void @xvinsve0_v4i64_h_0(ptr %d, ptr %a, ptr %b) nounwind {
273+
; CHECK-LABEL: xvinsve0_v4i64_h_0:
274+
; CHECK: # %bb.0: # %entry
275+
; CHECK-NEXT: xvld $xr0, $a1, 0
276+
; CHECK-NEXT: xvld $xr1, $a2, 0
277+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI9_0)
278+
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI9_0)
279+
; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0
280+
; CHECK-NEXT: xvst $xr2, $a0, 0
281+
; CHECK-NEXT: ret
282+
entry:
283+
%va = load <4 x i64>, ptr %a
284+
%vb = load <4 x i64>, ptr %b
285+
%vc = shufflevector <4 x i64> %va, <4 x i64> %vb, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
286+
store <4 x i64> %vc, ptr %d
287+
ret void
288+
}
289+
290+
define void @xvinsve0_v4i64_h_2(ptr %d, ptr %a, ptr %b) nounwind {
291+
; LA32-LABEL: xvinsve0_v4i64_h_2:
292+
; LA32: # %bb.0: # %entry
293+
; LA32-NEXT: xvld $xr0, $a1, 0
294+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 0
295+
; LA32-NEXT: xvld $xr1, $a2, 0
296+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 0
297+
; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 1
298+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 1
299+
; LA32-NEXT: xvpickve2gr.w $a1, $xr1, 6
300+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 2
301+
; LA32-NEXT: xvpickve2gr.w $a1, $xr1, 7
302+
; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 3
303+
; LA32-NEXT: xvpickve2gr.w $a1, $xr1, 0
304+
; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
305+
; LA32-NEXT: xvpickve2gr.w $a1, $xr1, 1
306+
; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
307+
; LA32-NEXT: xvpickve2gr.w $a1, $xr1, 2
308+
; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2
309+
; LA32-NEXT: xvpickve2gr.w $a1, $xr1, 3
310+
; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 3
311+
; LA32-NEXT: xvpermi.q $xr0, $xr2, 2
312+
; LA32-NEXT: xvst $xr0, $a0, 0
313+
; LA32-NEXT: ret
314+
;
315+
; LA64-LABEL: xvinsve0_v4i64_h_2:
316+
; LA64: # %bb.0: # %entry
317+
; LA64-NEXT: ld.d $a1, $a1, 0
318+
; LA64-NEXT: xvld $xr0, $a2, 0
319+
; LA64-NEXT: vinsgr2vr.d $vr1, $a1, 0
320+
; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 3
321+
; LA64-NEXT: vinsgr2vr.d $vr1, $a1, 1
322+
; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 0
323+
; LA64-NEXT: vinsgr2vr.d $vr2, $a1, 0
324+
; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 1
325+
; LA64-NEXT: vinsgr2vr.d $vr2, $a1, 1
326+
; LA64-NEXT: xvpermi.q $xr2, $xr1, 2
327+
; LA64-NEXT: xvst $xr2, $a0, 0
328+
; LA64-NEXT: ret
329+
entry:
330+
%va = load <4 x i64>, ptr %a
331+
%vb = load <4 x i64>, ptr %b
332+
%vc = shufflevector <4 x i64> %va, <4 x i64> %vb, <4 x i32> <i32 4, i32 5, i32 0, i32 7>
333+
store <4 x i64> %vc, ptr %d
334+
ret void
335+
}
336+
337+
define void @xvinsve0_v4f64_h(ptr %d, ptr %a, ptr %b) nounwind {
338+
; CHECK-LABEL: xvinsve0_v4f64_h:
339+
; CHECK: # %bb.0: # %entry
340+
; CHECK-NEXT: xvld $xr0, $a1, 0
341+
; CHECK-NEXT: xvld $xr1, $a2, 0
342+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
343+
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI11_0)
344+
; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0
345+
; CHECK-NEXT: xvst $xr2, $a0, 0
346+
; CHECK-NEXT: ret
347+
entry:
348+
%va = load <4 x double>, ptr %a
349+
%vb = load <4 x double>, ptr %b
350+
%vc = shufflevector <4 x double> %va, <4 x double> %vb, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
351+
store <4 x double> %vc, ptr %d
352+
ret void
353+
}

0 commit comments

Comments
 (0)