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[MIR] Serialize virtual register flags (#110228)
[MIR] Serialize virtual register flags This introduces target-specific vreg flag serialization. Flags are represented as `uint8_t` and the `TargetRegisterInfo` override provides methods `getVRegFlagValue` to deserialize and `getVRegFlagsOfReg` to serialize.
1 parent d6827f6 commit dbfca24

32 files changed

+290
-232
lines changed

‎llvm/include/llvm/CodeGen/MIRParser/MIParser.h‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -37,16 +37,15 @@ class TargetRegisterClass;
3737
class TargetSubtargetInfo;
3838

3939
struct VRegInfo {
40-
enum uint8_t {
41-
UNKNOWN, NORMAL, GENERIC, REGBANK
42-
} Kind = UNKNOWN;
40+
enum : uint8_t { UNKNOWN, NORMAL, GENERIC, REGBANK } Kind = UNKNOWN;
4341
bool Explicit = false; ///< VReg was explicitly specified in the .mir file.
4442
union {
4543
const TargetRegisterClass *RC;
4644
const RegisterBank *RegBank;
4745
} D;
4846
Register VReg;
4947
Register PreferredReg;
48+
std::vector<uint8_t> Flags;
5049
};
5150

5251
using Name2RegClassMap = StringMap<const TargetRegisterClass *>;
@@ -150,6 +149,8 @@ struct PerTargetMIParsingState {
150149
/// Return null if the name isn't a register bank.
151150
const RegisterBank *getRegBank(StringRef Name);
152151

152+
bool getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const;
153+
153154
PerTargetMIParsingState(const TargetSubtargetInfo &STI)
154155
: Subtarget(STI) {
155156
initNames2RegClasses();

‎llvm/include/llvm/CodeGen/MIRYamlMapping.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -191,6 +191,7 @@ struct VirtualRegisterDefinition {
191191
UnsignedValue ID;
192192
StringValue Class;
193193
StringValue PreferredRegister;
194+
std::vector<FlowStringValue> RegisterFlags;
194195

195196
// TODO: Serialize the target specific register hints.
196197

@@ -206,6 +207,8 @@ template <> struct MappingTraits<VirtualRegisterDefinition> {
206207
YamlIO.mapRequired("class", Reg.Class);
207208
YamlIO.mapOptional("preferred-register", Reg.PreferredRegister,
208209
StringValue()); // Don't print out when it's empty.
210+
YamlIO.mapOptional("flags", Reg.RegisterFlags,
211+
std::vector<FlowStringValue>());
209212
}
210213

211214
static const bool flow = true;

‎llvm/include/llvm/CodeGen/TargetRegisterInfo.h‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1213,6 +1213,15 @@ class TargetRegisterInfo : public MCRegisterInfo {
12131213
virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const {
12141214
return false;
12151215
}
1216+
1217+
virtual std::optional<uint8_t> getVRegFlagValue(StringRef Name) const {
1218+
return {};
1219+
}
1220+
1221+
virtual SmallVector<StringLiteral>
1222+
getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const {
1223+
return {};
1224+
}
12161225
};
12171226

12181227
//===----------------------------------------------------------------------===//

‎llvm/lib/CodeGen/MIRParser/MIParser.cpp‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -127,6 +127,16 @@ bool PerTargetMIParsingState::getRegisterByName(StringRef RegName,
127127
return false;
128128
}
129129

130+
bool PerTargetMIParsingState::getVRegFlagValue(StringRef FlagName,
131+
uint8_t &FlagValue) const {
132+
const auto *TRI = Subtarget.getRegisterInfo();
133+
std::optional<uint8_t> FV = TRI->getVRegFlagValue(FlagName);
134+
if (!FV)
135+
return true;
136+
FlagValue = *FV;
137+
return false;
138+
}
139+
130140
void PerTargetMIParsingState::initNames2InstrOpCodes() {
131141
if (!Names2InstrOpCodes.empty())
132142
return;

‎llvm/lib/CodeGen/MIRParser/MIRParser.cpp‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -696,6 +696,15 @@ bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
696696
VReg.PreferredRegister.Value, Error))
697697
return error(Error, VReg.PreferredRegister.SourceRange);
698698
}
699+
700+
for (const auto &FlagStringValue : VReg.RegisterFlags) {
701+
uint8_t FlagValue;
702+
if (Target->getVRegFlagValue(FlagStringValue.Value, FlagValue))
703+
return error(FlagStringValue.SourceRange.Start,
704+
Twine("use of undefined register flag '") +
705+
FlagStringValue.Value + "'");
706+
Info.Flags.push_back(FlagValue);
707+
}
699708
}
700709

701710
// Parse the liveins.

‎llvm/lib/CodeGen/MIRPrinter.cpp‎

Lines changed: 20 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -113,7 +113,8 @@ class MIRPrinter {
113113

114114
void print(const MachineFunction &MF);
115115

116-
void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
116+
void convert(yaml::MachineFunction &YamlMF, const MachineFunction &MF,
117+
const MachineRegisterInfo &RegInfo,
117118
const TargetRegisterInfo *TRI);
118119
void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
119120
const MachineFrameInfo &MFI);
@@ -231,7 +232,7 @@ void MIRPrinter::print(const MachineFunction &MF) {
231232
YamlMF.NoVRegs = MF.getProperties().hasProperty(
232233
MachineFunctionProperties::Property::NoVRegs);
233234

234-
convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
235+
convert(YamlMF, MF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
235236
MachineModuleSlotTracker MST(MMI, &MF);
236237
MST.incorporateFunction(MF.getFunction());
237238
convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
@@ -316,10 +317,21 @@ printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
316317
}
317318
}
318319

319-
void MIRPrinter::convert(yaml::MachineFunction &MF,
320+
static void printRegFlags(Register Reg,
321+
std::vector<yaml::FlowStringValue> &RegisterFlags,
322+
const MachineFunction &MF,
323+
const TargetRegisterInfo *TRI) {
324+
auto FlagValues = TRI->getVRegFlagsOfReg(Reg, MF);
325+
for (auto &Flag : FlagValues) {
326+
RegisterFlags.push_back(yaml::FlowStringValue(Flag.str()));
327+
}
328+
}
329+
330+
void MIRPrinter::convert(yaml::MachineFunction &YamlMF,
331+
const MachineFunction &MF,
320332
const MachineRegisterInfo &RegInfo,
321333
const TargetRegisterInfo *TRI) {
322-
MF.TracksRegLiveness = RegInfo.tracksLiveness();
334+
YamlMF.TracksRegLiveness = RegInfo.tracksLiveness();
323335

324336
// Print the virtual register definitions.
325337
for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
@@ -332,7 +344,8 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
332344
Register PreferredReg = RegInfo.getSimpleHint(Reg);
333345
if (PreferredReg)
334346
printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
335-
MF.VirtualRegisters.push_back(VReg);
347+
printRegFlags(Reg, VReg.RegisterFlags, MF, TRI);
348+
YamlMF.VirtualRegisters.push_back(VReg);
336349
}
337350

338351
// Print the live ins.
@@ -341,7 +354,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
341354
printRegMIR(LI.first, LiveIn.Register, TRI);
342355
if (LI.second)
343356
printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
344-
MF.LiveIns.push_back(LiveIn);
357+
YamlMF.LiveIns.push_back(LiveIn);
345358
}
346359

347360
// Prints the callee saved registers.
@@ -353,7 +366,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
353366
printRegMIR(*I, Reg, TRI);
354367
CalleeSavedRegisters.push_back(Reg);
355368
}
356-
MF.CalleeSavedRegisters = CalleeSavedRegisters;
369+
YamlMF.CalleeSavedRegisters = CalleeSavedRegisters;
357370
}
358371
}
359372

‎llvm/test/CodeGen/AMDGPU/limit-coalesce.mir‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2,13 +2,13 @@
22

33
# Check that coalescer does not create wider register tuple than in source
44

5-
# CHECK: - { id: 2, class: vreg_64, preferred-register: '' }
6-
# CHECK: - { id: 3, class: vreg_64, preferred-register: '' }
7-
# CHECK: - { id: 4, class: vreg_64, preferred-register: '' }
8-
# CHECK: - { id: 5, class: vreg_96, preferred-register: '' }
9-
# CHECK: - { id: 6, class: vreg_96, preferred-register: '' }
10-
# CHECK: - { id: 7, class: vreg_128, preferred-register: '' }
11-
# CHECK: - { id: 8, class: vreg_128, preferred-register: '' }
5+
# CHECK: - { id: 2, class: vreg_64, preferred-register: '', flags: [ ] }
6+
# CHECK: - { id: 3, class: vreg_64, preferred-register: '', flags: [ ] }
7+
# CHECK: - { id: 4, class: vreg_64, preferred-register: '', flags: [ ] }
8+
# CHECK: - { id: 5, class: vreg_96, preferred-register: '', flags: [ ] }
9+
# CHECK: - { id: 6, class: vreg_96, preferred-register: '', flags: [ ] }
10+
# CHECK: - { id: 7, class: vreg_128, preferred-register: '', flags: [ ] }
11+
# CHECK: - { id: 8, class: vreg_128, preferred-register: '', flags: [ ] }
1212
# No more registers shall be defined
1313
# CHECK-NEXT: liveins:
1414
# CHECK: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %4,

‎llvm/test/CodeGen/MIR/Generic/register-flag-error.mir‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
# RUN: not llc -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=ERR
2+
3+
---
4+
name: flags
5+
registers:
6+
- { id: 0, class: _, flags: [ 'VFLAG_ERR' ] }
7+
body: |
8+
bb.0:
9+
liveins: $w0
10+
%0 = G_ADD $w0, $w0
11+
...
12+
# ERR: use of undefined register flag
13+
# ERR: VFLAG_ERR

‎llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,8 @@ name: test
1414
tracksRegLiveness: true
1515
registers:
1616
- { id: 0, class: gr32 }
17-
# CHECK: - { id: 1, class: gr32, preferred-register: '%0' }
18-
# CHECK: - { id: 2, class: gr32, preferred-register: '$edi' }
17+
# CHECK: - { id: 1, class: gr32, preferred-register: '%0', flags: [ ] }
18+
# CHECK: - { id: 2, class: gr32, preferred-register: '$edi', flags: [ ] }
1919
- { id: 1, class: gr32, preferred-register: '%0' }
2020
- { id: 2, class: gr32, preferred-register: '$edi' }
2121
body: |

‎llvm/test/CodeGen/MIR/X86/generic-instr-type.mir‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -18,11 +18,11 @@
1818
---
1919
name: test_vregs
2020
# CHECK: registers:
21-
# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
22-
# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' }
23-
# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' }
24-
# CHECK-NEXT: - { id: 3, class: _, preferred-register: '' }
25-
# CHECK-NEXT: - { id: 4, class: _, preferred-register: '' }
21+
# CHECK-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
22+
# CHECK-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
23+
# CHECK-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
24+
# CHECK-NEXT: - { id: 3, class: _, preferred-register: '', flags: [ ] }
25+
# CHECK-NEXT: - { id: 4, class: _, preferred-register: '', flags: [ ] }
2626
registers:
2727
- { id: 0, class: _ }
2828
- { id: 1, class: _ }

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