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[Codegen] Add a separate stack ID for scalable predicates
This splits out "ScalablePredVector" from the "ScalableVector" StackID this is primarily to allow easy differentiation between vectors and predicates (without inspecting instructions). This new stack ID is not used in many places yet, but will be used in a later patch to mark stack slots that are known to contain predicates. Change-Id: I92c4c96af517ab2cfcf0a6eb9a853c2bac9de342
1 parent 924bf24 commit d4a5ccc

17 files changed

+71
-54
lines changed

‎llvm/include/llvm/CodeGen/MIRYamlMapping.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -378,6 +378,8 @@ struct ScalarEnumerationTraits<TargetStackID::Value> {
378378
IO.enumCase(ID, "default", TargetStackID::Default);
379379
IO.enumCase(ID, "sgpr-spill", TargetStackID::SGPRSpill);
380380
IO.enumCase(ID, "scalable-vector", TargetStackID::ScalableVector);
381+
IO.enumCase(ID, "scalable-predicate-vector",
382+
TargetStackID::ScalablePredicateVector);
381383
IO.enumCase(ID, "wasm-local", TargetStackID::WasmLocal);
382384
IO.enumCase(ID, "noalloc", TargetStackID::NoAlloc);
383385
}

‎llvm/include/llvm/CodeGen/MachineFrameInfo.h‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -494,7 +494,14 @@ class MachineFrameInfo {
494494
/// Should this stack ID be considered in MaxAlignment.
495495
bool contributesToMaxAlignment(uint8_t StackID) {
496496
return StackID == TargetStackID::Default ||
497-
StackID == TargetStackID::ScalableVector;
497+
StackID == TargetStackID::ScalableVector ||
498+
StackID == TargetStackID::ScalablePredicateVector;
499+
}
500+
501+
bool isScalableStackID(int ObjectIdx) const {
502+
uint8_t StackID = getStackID(ObjectIdx);
503+
return StackID == TargetStackID::ScalableVector ||
504+
StackID == TargetStackID::ScalablePredicateVector;
498505
}
499506

500507
/// setObjectAlignment - Change the alignment of the specified stack object.

‎llvm/include/llvm/CodeGen/TargetFrameLowering.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ enum Value {
3232
SGPRSpill = 1,
3333
ScalableVector = 2,
3434
WasmLocal = 3,
35+
ScalablePredicateVector = 4,
3536
NoAlloc = 255
3637
};
3738
}

‎llvm/lib/CodeGen/StackFrameLayoutAnalysisPass.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ struct StackFrameLayoutAnalysis {
7272
: Slot(Idx), Size(MFI.getObjectSize(Idx)),
7373
Align(MFI.getObjectAlign(Idx).value()), Offset(Offset),
7474
SlotTy(Invalid), Scalable(false) {
75-
Scalable = MFI.getStackID(Idx) == TargetStackID::ScalableVector;
75+
Scalable = MFI.isScalableStackID(Idx);
7676
if (MFI.isSpillSlotObjectIndex(Idx))
7777
SlotTy = SlotType::Spill;
7878
else if (MFI.isFixedObjectIndex(Idx))

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -329,7 +329,7 @@ static int64_t getArgumentStackToRestore(MachineFunction &MF,
329329
static bool produceCompactUnwindFrame(const AArch64FrameLowering &,
330330
MachineFunction &MF);
331331

332-
// Conservatively, returns true if the function is likely to have an SVE vectors
332+
// Conservatively, returns true if the function is likely to have SVE vectors
333333
// on the stack. This function is safe to be called before callee-saves or
334334
// object offsets have been determined.
335335
static bool isLikelyToHaveSVEStack(const AArch64FrameLowering &AFL,
@@ -343,7 +343,7 @@ static bool isLikelyToHaveSVEStack(const AArch64FrameLowering &AFL,
343343

344344
const MachineFrameInfo &MFI = MF.getFrameInfo();
345345
for (int FI = MFI.getObjectIndexBegin(); FI < MFI.getObjectIndexEnd(); FI++) {
346-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector)
346+
if (MFI.isScalableStackID(FI))
347347
return true;
348348
}
349349

@@ -726,8 +726,7 @@ static void emitCalleeSavedRestores(MachineBasicBlock &MBB,
726726
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameDestroy);
727727

728728
for (const auto &Info : CSI) {
729-
if (SVE !=
730-
(MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector))
729+
if (SVE != MFI.isScalableStackID(Info.getFrameIdx()))
731730
continue;
732731

733732
MCRegister Reg = Info.getReg();
@@ -2141,7 +2140,7 @@ AArch64FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
21412140
const auto *AFI = MF.getInfo<AArch64FunctionInfo>();
21422141
bool FPAfterSVECalleeSaves =
21432142
isTargetWindows(MF) && AFI->getSVECalleeSavedStackSize();
2144-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
2143+
if (MFI.isScalableStackID(FI)) {
21452144
if (FPAfterSVECalleeSaves &&
21462145
-ObjectOffset <= (int64_t)AFI->getSVECalleeSavedStackSize())
21472146
return StackOffset::getScalable(ObjectOffset);
@@ -2207,7 +2206,7 @@ StackOffset AArch64FrameLowering::resolveFrameIndexReference(
22072206
const auto &MFI = MF.getFrameInfo();
22082207
int64_t ObjectOffset = MFI.getObjectOffset(FI);
22092208
bool isFixed = MFI.isFixedObjectIndex(FI);
2210-
bool isSVE = MFI.getStackID(FI) == TargetStackID::ScalableVector;
2209+
bool isSVE = MFI.isScalableStackID(FI);
22112210
return resolveFrameOffsetReference(MF, ObjectOffset, isFixed, isSVE, FrameReg,
22122211
PreferFP, ForSimm);
22132212
}
@@ -2934,10 +2933,14 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
29342933
}
29352934
// Update the StackIDs of the SVE stack slots.
29362935
MachineFrameInfo &MFI = MF.getFrameInfo();
2937-
if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) {
2936+
if (RPI.Type == RegPairInfo::ZPR) {
29382937
MFI.setStackID(FrameIdxReg1, TargetStackID::ScalableVector);
29392938
if (RPI.isPaired())
29402939
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalableVector);
2940+
} else if (RPI.Type == RegPairInfo::PPR) {
2941+
MFI.setStackID(FrameIdxReg1, TargetStackID::ScalablePredicateVector);
2942+
if (RPI.isPaired())
2943+
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalablePredicateVector);
29412944
}
29422945
}
29432946
return true;
@@ -3145,8 +3148,7 @@ void AArch64FrameLowering::determineStackHazardSlot(
31453148
for (auto &MI : MBB) {
31463149
std::optional<int> FI = getLdStFrameID(MI, MFI);
31473150
if (FI && *FI >= 0 && *FI < (int)FrameObjects.size()) {
3148-
if (MFI.getStackID(*FI) == TargetStackID::ScalableVector ||
3149-
AArch64InstrInfo::isFpOrNEON(MI))
3151+
if (MFI.isScalableStackID(*FI) || AArch64InstrInfo::isFpOrNEON(MI))
31503152
FrameObjects[*FI] |= 2;
31513153
else
31523154
FrameObjects[*FI] |= 1;
@@ -3591,7 +3593,7 @@ static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
35913593
#ifndef NDEBUG
35923594
// First process all fixed stack objects.
35933595
for (int I = MFI.getObjectIndexBegin(); I != 0; ++I)
3594-
assert(MFI.getStackID(I) != TargetStackID::ScalableVector &&
3596+
assert(!MFI.isScalableStackID(I) &&
35953597
"SVE vectors should never be passed on the stack by value, only by "
35963598
"reference.");
35973599
#endif
@@ -3625,12 +3627,11 @@ static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
36253627
int StackProtectorFI = -1;
36263628
if (MFI.hasStackProtectorIndex()) {
36273629
StackProtectorFI = MFI.getStackProtectorIndex();
3628-
if (MFI.getStackID(StackProtectorFI) == TargetStackID::ScalableVector)
3630+
if (MFI.isScalableStackID(StackProtectorFI))
36293631
ObjectsToAllocate.push_back(StackProtectorFI);
36303632
}
36313633
for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) {
3632-
unsigned StackID = MFI.getStackID(I);
3633-
if (StackID != TargetStackID::ScalableVector)
3634+
if (!MFI.isScalableStackID(I))
36343635
continue;
36353636
if (I == StackProtectorFI)
36363637
continue;
@@ -4634,8 +4635,7 @@ void AArch64FrameLowering::orderFrameObjects(
46344635
if (AFI.hasStackHazardSlotIndex()) {
46354636
std::optional<int> FI = getLdStFrameID(MI, MFI);
46364637
if (FI && *FI >= 0 && *FI < (int)FrameObjects.size()) {
4637-
if (MFI.getStackID(*FI) == TargetStackID::ScalableVector ||
4638-
AArch64InstrInfo::isFpOrNEON(MI))
4638+
if (MFI.isScalableStackID(*FI) || AArch64InstrInfo::isFpOrNEON(MI))
46394639
FrameObjects[*FI].Accesses |= FrameObject::AccessFPR;
46404640
else
46414641
FrameObjects[*FI].Accesses |= FrameObject::AccessGPR;
@@ -4993,7 +4993,7 @@ void AArch64FrameLowering::emitRemarks(
49934993
}
49944994

49954995
unsigned RegTy = StackAccess::AccessType::GPR;
4996-
if (MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector) {
4996+
if (MFI.isScalableStackID(FrameIdx)) {
49974997
// SPILL_PPR_TO_ZPR_SLOT_PSEUDO and FILL_PPR_FROM_ZPR_SLOT_PSEUDO
49984998
// spill/fill the predicate as a data vector (so are an FPR access).
49994999
if (MI.getOpcode() != AArch64::SPILL_PPR_TO_ZPR_SLOT_PSEUDO &&

‎llvm/lib/Target/AArch64/AArch64FrameLowering.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,7 @@ class AArch64FrameLowering : public TargetFrameLowering {
123123
return false;
124124
case TargetStackID::Default:
125125
case TargetStackID::ScalableVector:
126+
case TargetStackID::ScalablePredicateVector:
126127
case TargetStackID::NoAlloc:
127128
return true;
128129
}
@@ -131,7 +132,8 @@ class AArch64FrameLowering : public TargetFrameLowering {
131132
bool isStackIdSafeForLocalArea(unsigned StackId) const override {
132133
// We don't support putting SVE objects into the pre-allocated local
133134
// frame block at the moment.
134-
return StackId != TargetStackID::ScalableVector;
135+
return (StackId != TargetStackID::ScalableVector &&
136+
StackId != TargetStackID::ScalablePredicateVector);
135137
}
136138

137139
friend class AArch64PrologueEmitter;

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7497,7 +7497,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
74977497
int FI = cast<FrameIndexSDNode>(N)->getIndex();
74987498
// We can only encode VL scaled offsets, so only fold in frame indexes
74997499
// referencing SVE objects.
7500-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
7500+
if (MFI.isScalableStackID(FI)) {
75017501
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
75027502
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i64);
75037503
return true;
@@ -7543,7 +7543,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
75437543
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
75447544
// We can only encode VL scaled offsets, so only fold in frame indexes
75457545
// referencing SVE objects.
7546-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector)
7546+
if (MFI.isScalableStackID(FI))
75477547
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
75487548
}
75497549

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9115,8 +9115,7 @@ void AArch64TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
91159115
(MI.getOpcode() == AArch64::ADDXri ||
91169116
MI.getOpcode() == AArch64::SUBXri)) {
91179117
const MachineOperand &MO = MI.getOperand(1);
9118-
if (MO.isFI() && MF.getFrameInfo().getStackID(MO.getIndex()) ==
9119-
TargetStackID::ScalableVector)
9118+
if (MO.isFI() && MF.getFrameInfo().isScalableStackID(MO.getIndex()))
91209119
MI.addOperand(MachineOperand::CreateReg(AArch64::VG, /*IsDef=*/false,
91219120
/*IsImplicit=*/true));
91229121
}
@@ -9565,8 +9564,12 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
95659564
Align Alignment = DAG.getDataLayout().getPrefTypeAlign(Ty);
95669565
MachineFrameInfo &MFI = MF.getFrameInfo();
95679566
int FI = MFI.CreateStackObject(StoreSize, Alignment, false);
9568-
if (isScalable)
9569-
MFI.setStackID(FI, TargetStackID::ScalableVector);
9567+
if (isScalable) {
9568+
bool IsPred = VA.getValVT() == MVT::aarch64svcount ||
9569+
VA.getValVT().getVectorElementType() == MVT::i1;
9570+
MFI.setStackID(FI, IsPred ? TargetStackID::ScalablePredicateVector
9571+
: TargetStackID::ScalableVector);
9572+
}
95709573

95719574
MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
95729575
SDValue Ptr = DAG.getFrameIndex(
@@ -29393,7 +29396,7 @@ void AArch64TargetLowering::finalizeLowering(MachineFunction &MF) const {
2939329396
// than doing it here in finalizeLowering.
2939429397
if (MFI.hasStackProtectorIndex()) {
2939529398
for (unsigned int i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
29396-
if (MFI.getStackID(i) == TargetStackID::ScalableVector &&
29399+
if (MFI.isScalableStackID(i) &&
2939729400
MFI.getObjectSSPLayout(i) != MachineFrameInfo::SSPLK_None) {
2939829401
MFI.setStackID(MFI.getStackProtectorIndex(),
2939929402
TargetStackID::ScalableVector);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5582,7 +5582,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
55825582
assert(Subtarget.isSVEorStreamingSVEAvailable() &&
55835583
"Unexpected register store without SVE store instructions");
55845584
Opc = AArch64::STR_PXI;
5585-
StackID = TargetStackID::ScalableVector;
5585+
StackID = TargetStackID::ScalablePredicateVector;
55865586
}
55875587
break;
55885588
}
@@ -5597,7 +5597,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
55975597
Opc = AArch64::STRSui;
55985598
else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
55995599
Opc = AArch64::STR_PPXI;
5600-
StackID = TargetStackID::ScalableVector;
5600+
StackID = TargetStackID::ScalablePredicateVector;
56015601
}
56025602
break;
56035603
case 8:
@@ -5767,7 +5767,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
57675767
if (IsPNR)
57685768
PNRReg = DestReg;
57695769
Opc = AArch64::LDR_PXI;
5770-
StackID = TargetStackID::ScalableVector;
5770+
StackID = TargetStackID::ScalablePredicateVector;
57715771
}
57725772
break;
57735773
}
@@ -5782,7 +5782,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
57825782
Opc = AArch64::LDRSui;
57835783
else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
57845784
Opc = AArch64::LDR_PPXI;
5785-
StackID = TargetStackID::ScalableVector;
5785+
StackID = TargetStackID::ScalablePredicateVector;
57865786
}
57875787
break;
57885788
case 8:

‎llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -739,7 +739,7 @@ void AArch64PrologueEmitter::emitCalleeSavedGPRLocations(
739739
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
740740
for (const auto &Info : CSI) {
741741
unsigned FrameIdx = Info.getFrameIdx();
742-
if (MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector)
742+
if (MFI.isScalableStackID(FrameIdx))
743743
continue;
744744

745745
assert(!Info.isSpilledToReg() && "Spilling to registers not implemented");
@@ -772,7 +772,7 @@ void AArch64PrologueEmitter::emitCalleeSavedSVELocations(
772772
}
773773

774774
for (const auto &Info : CSI) {
775-
if (MFI.getStackID(Info.getFrameIdx()) != TargetStackID::ScalableVector)
775+
if (!MFI.isScalableStackID(Info.getFrameIdx()))
776776
continue;
777777

778778
// Not all unwinders may know about SVE registers, so assume the lowest

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