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Address gaps in RISCV function unwinding
1 parent 556c846 commit d14ca45

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2 files changed

+27
-4
lines changed

2 files changed

+27
-4
lines changed

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1899,4 +1899,24 @@ RISCVSingleStepBreakpointLocationsPredictor::HandleAtomicSequence(
18991899
return bp_addrs;
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}
19011901

1902+
bool EmulateInstructionRISCV::CreateFunctionEntryUnwind(
1903+
UnwindPlan &unwind_plan) {
1904+
unwind_plan.Clear();
1905+
unwind_plan.SetRegisterKind(eRegisterKindLLDB);
1906+
1907+
UnwindPlan::Row row;
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1909+
// Our previous Call Frame Address is the stack pointer
1910+
row.GetCFAValue().SetIsRegisterPlusOffset(gpr_sp_riscv, 0);
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row.SetRegisterLocationToSame(gpr_fp_riscv, /*must_replace=*/false);
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1913+
unwind_plan.AppendRow(std::move(row));
1914+
unwind_plan.SetSourceName("EmulateInstructionRISCV");
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unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
1916+
unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolYes);
1917+
unwind_plan.SetUnwindPlanForSignalTrap(eLazyBoolNo);
1918+
unwind_plan.SetReturnAddressRegister(gpr_ra_riscv);
1919+
return true;
1920+
}
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} // namespace lldb_private

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -57,11 +57,12 @@ class EmulateInstructionRISCV : public EmulateInstruction {
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5858
static bool SupportsThisInstructionType(InstructionType inst_type) {
5959
switch (inst_type) {
60-
case eInstructionTypeAny:
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case eInstructionTypePCModifying:
60+
case lldb_private::eInstructionTypeAny:
61+
case lldb_private::eInstructionTypePrologueEpilogue:
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return true;
63-
case eInstructionTypePrologueEpilogue:
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case eInstructionTypeAll:
63+
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case lldb_private::eInstructionTypePCModifying:
65+
case lldb_private::eInstructionTypeAll:
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return false;
6667
}
6768
llvm_unreachable("Fully covered switch above!");
@@ -94,6 +95,8 @@ class EmulateInstructionRISCV : public EmulateInstruction {
9495
std::optional<RegisterInfo> GetRegisterInfo(lldb::RegisterKind reg_kind,
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uint32_t reg_num) override;
9697

98+
bool CreateFunctionEntryUnwind(UnwindPlan &unwind_plan) override;
99+
97100
std::optional<DecodeResult> ReadInstructionAt(lldb::addr_t addr);
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std::optional<DecodeResult> Decode(uint32_t inst);
99102
bool Execute(DecodeResult inst, bool ignore_cond);

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