fixup! [AArch64][llvm] Armv9.7-A: Add support for GICv5 (FEAT_GCIE)

jthackray · jthackray · commit ccda73d43fe5 · 2025-10-23T23:31:51.000+01:00
Optimisations suggested in CR.
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -2586,14 +2586,14 @@ foreach n=0-15 in {
 //===----------------------------------------------------------------------===//
 
 // GIC
-class GIC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, bit needsreg> {
+class GIC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2> {
   string Name = name;
   bits<14> Encoding;
   let Encoding{13-11} = op1;
   let Encoding{10-7} = crn;
   let Encoding{6-3} = crm;
   let Encoding{2-0} = op2;
-  bit NeedsReg = needsreg;
+  bit NeedsReg = 1;
   string RequiresStr = [{ {AArch64::FeatureGCIE} }];
 }
 
@@ -2609,14 +2609,14 @@ class GSB<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2> {
 }
 
 // GICR
-class GICR<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, bit needsreg> {
+class GICR<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2> {
   string Name = name;
   bits<14> Encoding;
   let Encoding{13-11} = op1;
   let Encoding{10-7} = crn;
   let Encoding{6-3} = crm;
   let Encoding{2-0} = op2;
-  bit NeedsReg = needsreg;
+  bit NeedsReg = 1;
   string RequiresStr = [{ {AArch64::FeatureGCIE} }];
 }
 
@@ -2666,31 +2666,33 @@ def lookupGICRByName : SearchIndex {
 def : GSB<"sys",      0b000, 0b1100, 0b0000, 0b000>;
 def : GSB<"ack",      0b000, 0b1100, 0b0000, 0b001>;
 
-//                    Op1    CRn     CRm     Op2    needsReg
-def : GIC<"cdaff",    0b000, 0b1100, 0b0001, 0b011, 1>;
-def : GIC<"cddi",     0b000, 0b1100, 0b0010, 0b000, 1>;
-def : GIC<"cddis",    0b000, 0b1100, 0b0001, 0b000, 1>;
-def : GIC<"cden",     0b000, 0b1100, 0b0001, 0b001, 1>;
-def : GIC<"cdeoi",    0b000, 0b1100, 0b0001, 0b111, 1>;
-def : GIC<"cdhm",     0b000, 0b1100, 0b0010, 0b001, 1>;
-def : GIC<"cdpend",   0b000, 0b1100, 0b0001, 0b100, 1>;
-def : GIC<"cdpri",    0b000, 0b1100, 0b0001, 0b010, 1>;
-def : GIC<"cdrcfg",   0b000, 0b1100, 0b0001, 0b101, 1>;
-def : GICR<"cdia",    0b000, 0b1100, 0b0011, 0b000, 1>;
-def : GICR<"cdnmia",  0b000, 0b1100, 0b0011, 0b001, 1>;
-def : GIC<"vdaff",    0b100, 0b1100, 0b0001, 0b011, 1>;
-def : GIC<"vddi",     0b100, 0b1100, 0b0010, 0b000, 1>;
-def : GIC<"vddis",    0b100, 0b1100, 0b0001, 0b000, 1>;
-def : GIC<"vden",     0b100, 0b1100, 0b0001, 0b001, 1>;
-def : GIC<"vdhm",     0b100, 0b1100, 0b0010, 0b001, 1>;
-def : GIC<"vdpend",   0b100, 0b1100, 0b0001, 0b100, 1>;
-def : GIC<"vdpri",    0b100, 0b1100, 0b0001, 0b010, 1>;
-def : GIC<"vdrcfg",   0b100, 0b1100, 0b0001, 0b101, 1>;
-def : GIC<"ldaff",    0b110, 0b1100, 0b0001, 0b011, 1>;
-def : GIC<"lddi",     0b110, 0b1100, 0b0010, 0b000, 1>;
-def : GIC<"lddis",    0b110, 0b1100, 0b0001, 0b000, 1>;
-def : GIC<"lden",     0b110, 0b1100, 0b0001, 0b001, 1>;
-def : GIC<"ldhm",     0b110, 0b1100, 0b0010, 0b001, 1>;
-def : GIC<"ldpend",   0b110, 0b1100, 0b0001, 0b100, 1>;
-def : GIC<"ldpri",    0b110, 0b1100, 0b0001, 0b010, 1>;
-def : GIC<"ldrcfg",   0b110, 0b1100, 0b0001, 0b101, 1>;
+//                    Op1    CRn     CRm     Op2
+def : GICR<"cdia",    0b000, 0b1100, 0b0011, 0b000>;
+def : GICR<"cdnmia",  0b000, 0b1100, 0b0011, 0b001>;
+
+//                    Op1    CRn     CRm     Op2
+def : GIC<"cdaff",    0b000, 0b1100, 0b0001, 0b011>;
+def : GIC<"cddi",     0b000, 0b1100, 0b0010, 0b000>;
+def : GIC<"cddis",    0b000, 0b1100, 0b0001, 0b000>;
+def : GIC<"cden",     0b000, 0b1100, 0b0001, 0b001>;
+def : GIC<"cdeoi",    0b000, 0b1100, 0b0001, 0b111>;
+def : GIC<"cdhm",     0b000, 0b1100, 0b0010, 0b001>;
+def : GIC<"cdpend",   0b000, 0b1100, 0b0001, 0b100>;
+def : GIC<"cdpri",    0b000, 0b1100, 0b0001, 0b010>;
+def : GIC<"cdrcfg",   0b000, 0b1100, 0b0001, 0b101>;
+def : GIC<"vdaff",    0b100, 0b1100, 0b0001, 0b011>;
+def : GIC<"vddi",     0b100, 0b1100, 0b0010, 0b000>;
+def : GIC<"vddis",    0b100, 0b1100, 0b0001, 0b000>;
+def : GIC<"vden",     0b100, 0b1100, 0b0001, 0b001>;
+def : GIC<"vdhm",     0b100, 0b1100, 0b0010, 0b001>;
+def : GIC<"vdpend",   0b100, 0b1100, 0b0001, 0b100>;
+def : GIC<"vdpri",    0b100, 0b1100, 0b0001, 0b010>;
+def : GIC<"vdrcfg",   0b100, 0b1100, 0b0001, 0b101>;
+def : GIC<"ldaff",    0b110, 0b1100, 0b0001, 0b011>;
+def : GIC<"lddi",     0b110, 0b1100, 0b0010, 0b000>;
+def : GIC<"lddis",    0b110, 0b1100, 0b0001, 0b000>;
+def : GIC<"lden",     0b110, 0b1100, 0b0001, 0b001>;
+def : GIC<"ldhm",     0b110, 0b1100, 0b0010, 0b001>;
+def : GIC<"ldpend",   0b110, 0b1100, 0b0001, 0b100>;
+def : GIC<"ldpri",    0b110, 0b1100, 0b0001, 0b010>;
+def : GIC<"ldrcfg",   0b110, 0b1100, 0b0001, 0b101>;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -4046,7 +4046,7 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
       setRequiredFeatureString(GIC->getRequiredFeatures(), Str);
       return TokError(Str);
     }
-    ExpectRegister = GIC->NeedsReg;
+    ExpectRegister = true;
     createSysAlias(GIC->Encoding, Operands, S);
   } else if (Mnemonic == "gsb") {
     const AArch64GSB::GSB *GSB = AArch64GSB::lookupGSBByName(Op);
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -1034,7 +1034,7 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
       if (!GIC || !GIC->haveFeatures(STI.getFeatureBits()))
         return false;
 
-      NeedsReg = GIC->NeedsReg;
+      NeedsReg = true;
       Ins = "gic\t";
       Name = std::string(GIC->Name);
     } else {
diff --git a/llvm/test/MC/AArch64/armv9.7a-gcie-diagnostics.s b/llvm/test/MC/AArch64/armv9.7a-gcie-diagnostics.s
@@ -0,0 +1,29 @@
+// RUN: not llvm-mc -triple=aarch64 -mattr=+gcie -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-REQUIRES-GCIE
+
+//------------------------------------------------------------------------------
+// FEAT_GCIE instructions
+//------------------------------------------------------------------------------
+
+gsb
+// CHECK-ERROR: error: invalid operand for GSB instruction
+
+gsb ack
+// CHECK-REQUIRES-GCIE: GSB ack requires: gcie
+
+gicr
+// CHECK-ERROR: error: expected register operand
+
+gicr x3, foo
+// CHECK-ERROR: error: invalid operand for GICR instruction
+
+gicr x3, cdnmia
+// CHECK-REQUIRES-GCIE: GICR cdnmia requires: gcie
+
+gic cdaff
+// CHECK-ERROR: error: specified gic op requires a register
+
+gic cdaff, x3
+// CHECK-REQUIRES-GCIE: GIC cdaff requires: gcie

Original file line number	Diff line number	Diff line change
`@@ -4046,7 +4046,7 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,`
`4046`	`4046`	`setRequiredFeatureString(GIC->getRequiredFeatures(), Str);`
`4047`	`4047`	`return TokError(Str);`
`4048`	`4048`	`}`
`4049`		`- ExpectRegister = GIC->NeedsReg;`
	`4049`	`+ ExpectRegister = true;`
`4050`	`4050`	`createSysAlias(GIC->Encoding, Operands, S);`
`4051`	`4051`	`} else if (Mnemonic == "gsb") {`
`4052`	`4052`	`const AArch64GSB::GSB *GSB = AArch64GSB::lookupGSBByName(Op);`