change bits<1> -> bits<0> in one place

s-barannikov · s-barannikov · commit cbbc47be594c · 2025-09-19T19:42:05.000+03:00
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -1272,7 +1272,7 @@ multiclass sme_vector_v_to_tile<string mnemonic, bit is_col> {
                                    is_col, sme_elm_idx0_0, ZPR128, mnemonic>,
                                    SMEPseudo2Instr<NAME # _Q, 1> {
     bits<4> ZAd;
-    bits<1> imm;
+    bits<0> imm;
     let Inst{3-0} = ZAd;
   }
 

Original file line number	Diff line number	Diff line change
`@@ -1272,7 +1272,7 @@ multiclass sme_vector_v_to_tile<string mnemonic, bit is_col> {`
`1272`	`1272`	`is_col, sme_elm_idx0_0, ZPR128, mnemonic>,`
`1273`	`1273`	`SMEPseudo2Instr<NAME # _Q, 1> {`
`1274`	`1274`	`bits<4> ZAd;`
`1275`		`- bits<1> imm;`
	`1275`	`+ bits<0> imm;`
`1276`	`1276`	`let Inst{3-0} = ZAd;`
`1277`	`1277`	`}`
`1278`	`1278`