Instruction selection wave 2

Author: QuantumSegfault

llvm/lib/Target/WebAssembly/CMakeLists.txt

@@ -7,13 +7,15 @@ tablegen(LLVM WebAssemblyGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM WebAssemblyGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM WebAssemblyGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM WebAssemblyGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM WebAssemblyGenGlobalISel.inc -gen-global-isel)
 tablegen(LLVM WebAssemblyGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM WebAssemblyGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM WebAssemblyGenRegisterBank.inc -gen-register-bank)
 tablegen(LLVM WebAssemblyGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM WebAssemblyGenSubtargetInfo.inc -gen-subtarget)
 
+set(LLVM_TARGET_DEFINITIONS WebAssemblyGISel.td)
+tablegen(LLVM WebAssemblyGenGlobalISel.inc -gen-global-isel)
+
 add_public_tablegen_target(WebAssemblyCommonTableGen)
 
 add_llvm_target(WebAssemblyCodeGen

llvm/lib/Target/WebAssembly/GISel/WebAssemblyCallLowering.cpp

@@ -527,7 +527,8 @@ bool WebAssemblyCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
         auto NewOutReg = Arg.Regs[Part];
         if (!RBI.constrainGenericRegister(NewOutReg, NewRegClass, MRI)) {
           NewOutReg = MRI.createGenericVirtualRegister(NewLLT);
-          assert(RBI.constrainGenericRegister(NewOutReg, NewRegClass, MRI) && "Couldn't constrain brand-new register?");
+          assert(RBI.constrainGenericRegister(NewOutReg, NewRegClass, MRI) &&
+                 "Couldn't constrain brand-new register?");
           MIRBuilder.buildCopy(NewOutReg, Arg.Regs[Part]);
         }
         MIB.addUse(NewOutReg);
@@ -704,9 +705,12 @@ bool WebAssemblyCallLowering::lowerFormalArguments(
         getLLTForType(*PointerType::get(Ctx, 0), DL));
     MFI->setVarargBufferVreg(VarargVreg);
 
-    MIRBuilder.buildInstr(getWASMArgOpcode(PtrVT))
-        .addDef(VarargVreg)
-        .addImm(FinalArgIdx);
+    auto ArgInst = MIRBuilder.buildInstr(getWASMArgOpcode(PtrVT))
+                       .addDef(VarargVreg)
+                       .addImm(FinalArgIdx);
+
+    constrainOperandRegClass(MF, TRI, MRI, TII, RBI, *ArgInst,
+                             ArgInst->getDesc(), ArgInst->getOperand(0), 0);
 
     MFI->addParam(PtrVT);
     ++FinalArgIdx;
@@ -911,7 +915,8 @@ bool WebAssemblyCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
           auto NewRetReg = Ret.Regs[Part];
           if (!RBI.constrainGenericRegister(NewRetReg, NewRegClass, MRI)) {
             NewRetReg = MRI.createGenericVirtualRegister(NewLLT);
-            assert(RBI.constrainGenericRegister(NewRetReg, NewRegClass, MRI) && "Couldn't constrain brand-new register?");
+            assert(RBI.constrainGenericRegister(NewRetReg, NewRegClass, MRI) &&
+                   "Couldn't constrain brand-new register?");
             MIRBuilder.buildCopy(NewRetReg, Ret.Regs[Part]);
           }
           CallInst.addDef(Ret.Regs[Part]);