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[Alignment][NFC] Use Align in SelectionDAG::getMemIntrinsicNode
Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: jholewinski, nemanjai, hiraditya, kbarton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77149
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+146
-149
lines changed

9 files changed

+146
-149
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAG.h‎

Lines changed: 30 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1114,14 +1114,36 @@ class SelectionDAG {
11141114
/// INTRINSIC_W_CHAIN, or a target-specific opcode with a value not
11151115
/// less than FIRST_TARGET_MEMORY_OPCODE.
11161116
SDValue getMemIntrinsicNode(
1117-
unsigned Opcode, const SDLoc &dl, SDVTList VTList,
1118-
ArrayRef<SDValue> Ops, EVT MemVT,
1119-
MachinePointerInfo PtrInfo,
1120-
unsigned Align = 0,
1121-
MachineMemOperand::Flags Flags
1122-
= MachineMemOperand::MOLoad | MachineMemOperand::MOStore,
1123-
uint64_t Size = 0,
1124-
const AAMDNodes &AAInfo = AAMDNodes());
1117+
unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
1118+
EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
1119+
MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad |
1120+
MachineMemOperand::MOStore,
1121+
uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes());
1122+
1123+
inline SDValue getMemIntrinsicNode(
1124+
unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
1125+
EVT MemVT, MachinePointerInfo PtrInfo, MaybeAlign Alignment = None,
1126+
MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad |
1127+
MachineMemOperand::MOStore,
1128+
uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) {
1129+
// Ensure that codegen never sees alignment 0
1130+
return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo,
1131+
Alignment.getValueOr(getEVTAlign(MemVT)), Flags,
1132+
Size, AAInfo);
1133+
}
1134+
1135+
LLVM_ATTRIBUTE_DEPRECATED(
1136+
inline SDValue getMemIntrinsicNode(
1137+
unsigned Opcode, const SDLoc &dl, SDVTList VTList,
1138+
ArrayRef<SDValue> Ops, EVT MemVT, MachinePointerInfo PtrInfo,
1139+
unsigned Alignment,
1140+
MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad |
1141+
MachineMemOperand::MOStore,
1142+
uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()),
1143+
"") {
1144+
return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo,
1145+
MaybeAlign(Alignment), Flags, Size, AAInfo);
1146+
}
11251147

11261148
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList,
11271149
ArrayRef<SDValue> Ops, EVT MemVT,

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6679,17 +6679,16 @@ SDValue SelectionDAG::getMergeValues(ArrayRef<SDValue> Ops, const SDLoc &dl) {
66796679

66806680
SDValue SelectionDAG::getMemIntrinsicNode(
66816681
unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
6682-
EVT MemVT, MachinePointerInfo PtrInfo, unsigned Alignment,
6682+
EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
66836683
MachineMemOperand::Flags Flags, uint64_t Size, const AAMDNodes &AAInfo) {
66846684
if (!Size && MemVT.isScalableVector())
66856685
Size = MemoryLocation::UnknownSize;
66866686
else if (!Size)
66876687
Size = MemVT.getStoreSize();
66886688

66896689
MachineFunction &MF = getMachineFunction();
6690-
MachineMemOperand *MMO = MF.getMachineMemOperand(
6691-
PtrInfo, Flags, Size, Alignment ? Align(Alignment) : getEVTAlign(MemVT),
6692-
AAInfo);
6690+
MachineMemOperand *MMO =
6691+
MF.getMachineMemOperand(PtrInfo, Flags, Size, Alignment, AAInfo);
66936692

66946693
return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, MMO);
66956694
}

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp‎

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4713,10 +4713,10 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
47134713
// This is target intrinsic that touches memory
47144714
AAMDNodes AAInfo;
47154715
I.getAAMetadata(AAInfo);
4716-
Result = DAG.getMemIntrinsicNode(
4717-
Info.opc, getCurSDLoc(), VTs, Ops, Info.memVT,
4718-
MachinePointerInfo(Info.ptrVal, Info.offset),
4719-
Info.align ? Info.align->value() : 0, Info.flags, Info.size, AAInfo);
4716+
Result =
4717+
DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs, Ops, Info.memVT,
4718+
MachinePointerInfo(Info.ptrVal, Info.offset),
4719+
Info.align, Info.flags, Info.size, AAInfo);
47204720
} else if (!HasChain) {
47214721
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
47224722
} else if (!I.getType()->isVoidTy()) {
@@ -6529,12 +6529,10 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
65296529
Ops[2] = getValue(I.getArgOperand(1));
65306530
Ops[3] = getValue(I.getArgOperand(2));
65316531
Ops[4] = getValue(I.getArgOperand(3));
6532-
SDValue Result = DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
6533-
DAG.getVTList(MVT::Other), Ops,
6534-
EVT::getIntegerVT(*Context, 8),
6535-
MachinePointerInfo(I.getArgOperand(0)),
6536-
0, /* align */
6537-
Flags);
6532+
SDValue Result = DAG.getMemIntrinsicNode(
6533+
ISD::PREFETCH, sdl, DAG.getVTList(MVT::Other), Ops,
6534+
EVT::getIntegerVT(*Context, 8), MachinePointerInfo(I.getArgOperand(0)),
6535+
/* align */ None, Flags);
65386536

65396537
// Chain the prefetch in parallell with any pending loads, to stay out of
65406538
// the way of later optimizations.

‎llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp‎

Lines changed: 38 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -218,11 +218,10 @@ static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL,
218218
// covered by the vector op. Otherwise, it returns 1.
219219
static unsigned CanMergeParamLoadStoresStartingAt(
220220
unsigned Idx, uint32_t AccessSize, const SmallVectorImpl<EVT> &ValueVTs,
221-
const SmallVectorImpl<uint64_t> &Offsets, unsigned ParamAlignment) {
222-
assert(isPowerOf2_32(AccessSize) && "must be a power of 2!");
221+
const SmallVectorImpl<uint64_t> &Offsets, Align ParamAlignment) {
223222

224223
// Can't vectorize if param alignment is not sufficient.
225-
if (AccessSize > ParamAlignment)
224+
if (ParamAlignment < AccessSize)
226225
return 1;
227226
// Can't vectorize if offset is not aligned.
228227
if (Offsets[Idx] & (AccessSize - 1))
@@ -282,7 +281,7 @@ enum ParamVectorizationFlags {
282281
static SmallVector<ParamVectorizationFlags, 16>
283282
VectorizePTXValueVTs(const SmallVectorImpl<EVT> &ValueVTs,
284283
const SmallVectorImpl<uint64_t> &Offsets,
285-
unsigned ParamAlignment) {
284+
Align ParamAlignment) {
286285
// Set vector size to match ValueVTs and mark all elements as
287286
// scalars by default.
288287
SmallVector<ParamVectorizationFlags, 16> VectorInfo;
@@ -1243,7 +1242,7 @@ NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12431242

12441243
std::string NVPTXTargetLowering::getPrototype(
12451244
const DataLayout &DL, Type *retTy, const ArgListTy &Args,
1246-
const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment,
1245+
const SmallVectorImpl<ISD::OutputArg> &Outs, MaybeAlign retAlignment,
12471246
ImmutableCallSite CS) const {
12481247
auto PtrVT = getPointerTy(DL);
12491248

@@ -1279,8 +1278,8 @@ std::string NVPTXTargetLowering::getPrototype(
12791278
O << ".param .b" << PtrVT.getSizeInBits() << " _";
12801279
} else if (retTy->isAggregateType() || retTy->isVectorTy() ||
12811280
retTy->isIntegerTy(128)) {
1282-
O << ".param .align " << retAlignment << " .b8 _["
1283-
<< DL.getTypeAllocSize(retTy) << "]";
1281+
O << ".param .align " << (retAlignment ? retAlignment->value() : 0)
1282+
<< " .b8 _[" << DL.getTypeAllocSize(retTy) << "]";
12841283
} else {
12851284
llvm_unreachable("Unknown return type");
12861285
}
@@ -1353,16 +1352,16 @@ std::string NVPTXTargetLowering::getPrototype(
13531352
return O.str();
13541353
}
13551354

1356-
unsigned NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
1357-
ImmutableCallSite CS,
1358-
Type *Ty, unsigned Idx,
1359-
const DataLayout &DL) const {
1355+
Align NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
1356+
ImmutableCallSite CS, Type *Ty,
1357+
unsigned Idx,
1358+
const DataLayout &DL) const {
13601359
if (!CS) {
13611360
// CallSite is zero, fallback to ABI type alignment
1362-
return DL.getABITypeAlignment(Ty);
1361+
return DL.getABITypeAlign(Ty);
13631362
}
13641363

1365-
unsigned Align = 0;
1364+
unsigned Alignment = 0;
13661365
const Value *DirectCallee = CS.getCalledFunction();
13671366

13681367
if (!DirectCallee) {
@@ -1374,8 +1373,8 @@ unsigned NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
13741373
// With bitcast'd call targets, the instruction will be the call
13751374
if (isa<CallInst>(CalleeI)) {
13761375
// Check if we have call alignment metadata
1377-
if (getAlign(*cast<CallInst>(CalleeI), Idx, Align))
1378-
return Align;
1376+
if (getAlign(*cast<CallInst>(CalleeI), Idx, Alignment))
1377+
return Align(Alignment);
13791378

13801379
const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
13811380
// Ignore any bitcast instructions
@@ -1397,12 +1396,12 @@ unsigned NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
13971396
// Check for function alignment information if we found that the
13981397
// ultimate target is a Function
13991398
if (DirectCallee)
1400-
if (getAlign(*cast<Function>(DirectCallee), Idx, Align))
1401-
return Align;
1399+
if (getAlign(*cast<Function>(DirectCallee), Idx, Alignment))
1400+
return Align(Alignment);
14021401

14031402
// Call is indirect or alignment information is not available, fall back to
14041403
// the ABI type alignment
1405-
return DL.getABITypeAlignment(Ty);
1404+
return DL.getABITypeAlign(Ty);
14061405
}
14071406

14081407
SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
@@ -1450,15 +1449,14 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
14501449
SmallVector<EVT, 16> VTs;
14511450
SmallVector<uint64_t, 16> Offsets;
14521451
ComputePTXValueVTs(*this, DL, Ty, VTs, &Offsets);
1453-
unsigned ArgAlign =
1454-
getArgumentAlignment(Callee, CS, Ty, paramCount + 1, DL);
1452+
Align ArgAlign = getArgumentAlignment(Callee, CS, Ty, paramCount + 1, DL);
14551453
unsigned AllocSize = DL.getTypeAllocSize(Ty);
14561454
SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
14571455
bool NeedAlign; // Does argument declaration specify alignment?
14581456
if (Ty->isAggregateType() || Ty->isVectorTy() || Ty->isIntegerTy(128)) {
14591457
// declare .param .align <align> .b8 .param<n>[<size>];
14601458
SDValue DeclareParamOps[] = {
1461-
Chain, DAG.getConstant(ArgAlign, dl, MVT::i32),
1459+
Chain, DAG.getConstant(ArgAlign.value(), dl, MVT::i32),
14621460
DAG.getConstant(paramCount, dl, MVT::i32),
14631461
DAG.getConstant(AllocSize, dl, MVT::i32), InFlag};
14641462
Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
@@ -1539,8 +1537,9 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
15391537
// Adjust type of the store op if we've extended the scalar
15401538
// return value.
15411539
EVT TheStoreType = ExtendIntegerParam ? MVT::i32 : VTs[j];
1542-
unsigned EltAlign =
1543-
NeedAlign ? GreatestCommonDivisor64(ArgAlign, Offsets[j]) : 0;
1540+
MaybeAlign EltAlign;
1541+
if (NeedAlign)
1542+
EltAlign = commonAlignment(ArgAlign, Offsets[j]);
15441543

15451544
Chain = DAG.getMemIntrinsicNode(
15461545
Op, dl, DAG.getVTList(MVT::Other, MVT::Glue), StoreOperands,
@@ -1604,18 +1603,17 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
16041603
DAG.getConstant(paramCount, dl, MVT::i32),
16051604
DAG.getConstant(curOffset, dl, MVT::i32),
16061605
theVal, InFlag };
1607-
Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
1608-
CopyParamOps, elemtype,
1609-
MachinePointerInfo(), /* Align */ 0,
1610-
MachineMemOperand::MOStore);
1606+
Chain = DAG.getMemIntrinsicNode(
1607+
NVPTXISD::StoreParam, dl, CopyParamVTs, CopyParamOps, elemtype,
1608+
MachinePointerInfo(), /* Align */ None, MachineMemOperand::MOStore);
16111609

16121610
InFlag = Chain.getValue(1);
16131611
}
16141612
++paramCount;
16151613
}
16161614

16171615
GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
1618-
unsigned retAlignment = 0;
1616+
MaybeAlign retAlignment = None;
16191617

16201618
// Handle Result
16211619
if (Ins.size() > 0) {
@@ -1644,11 +1642,12 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
16441642
InFlag = Chain.getValue(1);
16451643
} else {
16461644
retAlignment = getArgumentAlignment(Callee, CS, RetTy, 0, DL);
1645+
assert(retAlignment && "retAlignment is guaranteed to be set");
16471646
SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1648-
SDValue DeclareRetOps[] = { Chain,
1649-
DAG.getConstant(retAlignment, dl, MVT::i32),
1650-
DAG.getConstant(resultsz / 8, dl, MVT::i32),
1651-
DAG.getConstant(0, dl, MVT::i32), InFlag };
1647+
SDValue DeclareRetOps[] = {
1648+
Chain, DAG.getConstant(retAlignment->value(), dl, MVT::i32),
1649+
DAG.getConstant(resultsz / 8, dl, MVT::i32),
1650+
DAG.getConstant(0, dl, MVT::i32), InFlag};
16521651
Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
16531652
DeclareRetOps);
16541653
InFlag = Chain.getValue(1);
@@ -1754,7 +1753,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
17541753
ComputePTXValueVTs(*this, DL, RetTy, VTs, &Offsets, 0);
17551754
assert(VTs.size() == Ins.size() && "Bad value decomposition");
17561755

1757-
unsigned RetAlign = getArgumentAlignment(Callee, CS, RetTy, 0, DL);
1756+
Align RetAlign = getArgumentAlignment(Callee, CS, RetTy, 0, DL);
17581757
auto VectorInfo = VectorizePTXValueVTs(VTs, Offsets, RetAlign);
17591758

17601759
SmallVector<EVT, 6> LoadVTs;
@@ -1770,7 +1769,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
17701769
bool needTruncate = false;
17711770
EVT TheLoadType = VTs[i];
17721771
EVT EltType = Ins[i].VT;
1773-
unsigned EltAlign = GreatestCommonDivisor64(RetAlign, Offsets[i]);
1772+
Align EltAlign = commonAlignment(RetAlign, Offsets[i]);
17741773
if (ExtendIntegerRetVal) {
17751774
TheLoadType = MVT::i32;
17761775
EltType = MVT::i32;
@@ -2545,7 +2544,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
25452544
ComputePTXValueVTs(*this, DL, Ty, VTs, &Offsets, 0);
25462545
assert(VTs.size() > 0 && "Unexpected empty type.");
25472546
auto VectorInfo =
2548-
VectorizePTXValueVTs(VTs, Offsets, DL.getABITypeAlignment(Ty));
2547+
VectorizePTXValueVTs(VTs, Offsets, DL.getABITypeAlign(Ty));
25492548

25502549
SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
25512550
int VecIdx = -1; // Index of the first element of the current vector.
@@ -2664,7 +2663,7 @@ NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
26642663
assert(VTs.size() == OutVals.size() && "Bad return value decomposition");
26652664

26662665
auto VectorInfo = VectorizePTXValueVTs(
2667-
VTs, Offsets, RetTy->isSized() ? DL.getABITypeAlignment(RetTy) : 1);
2666+
VTs, Offsets, RetTy->isSized() ? DL.getABITypeAlign(RetTy) : Align(1));
26682667

26692668
// PTX Interoperability Guide 3.3(A): [Integer] Values shorter than
26702669
// 32-bits are sign extended or zero extended, depending on whether
@@ -2716,10 +2715,9 @@ NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
27162715
// Adjust type of load/store op if we've extended the scalar
27172716
// return value.
27182717
EVT TheStoreType = ExtendIntegerRetVal ? MVT::i32 : VTs[i];
2719-
Chain = DAG.getMemIntrinsicNode(Op, dl, DAG.getVTList(MVT::Other),
2720-
StoreOperands, TheStoreType,
2721-
MachinePointerInfo(), /* Align */ 1,
2722-
MachineMemOperand::MOStore);
2718+
Chain = DAG.getMemIntrinsicNode(
2719+
Op, dl, DAG.getVTList(MVT::Other), StoreOperands, TheStoreType,
2720+
MachinePointerInfo(), Align(1), MachineMemOperand::MOStore);
27232721
// Cleanup vector state.
27242722
StoreOperands.clear();
27252723
}

‎llvm/lib/Target/NVPTX/NVPTXISelLowering.h‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -491,8 +491,7 @@ class NVPTXTargetLowering : public TargetLowering {
491491

492492
std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &,
493493
const SmallVectorImpl<ISD::OutputArg> &,
494-
unsigned retAlignment,
495-
ImmutableCallSite CS) const;
494+
MaybeAlign retAlignment, ImmutableCallSite CS) const;
496495

497496
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
498497
const SmallVectorImpl<ISD::OutputArg> &Outs,
@@ -579,8 +578,8 @@ class NVPTXTargetLowering : public TargetLowering {
579578
SelectionDAG &DAG) const override;
580579
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
581580

582-
unsigned getArgumentAlignment(SDValue Callee, ImmutableCallSite CS, Type *Ty,
583-
unsigned Idx, const DataLayout &DL) const;
581+
Align getArgumentAlignment(SDValue Callee, ImmutableCallSite CS, Type *Ty,
582+
unsigned Idx, const DataLayout &DL) const;
584583
};
585584
} // namespace llvm
586585

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2750,7 +2750,7 @@ SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
27502750
SDValue Ops[] = { GA, Reg };
27512751
return DAG.getMemIntrinsicNode(
27522752
PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2753-
MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0,
2753+
MachinePointerInfo::getGOT(DAG.getMachineFunction()), None,
27542754
MachineMemOperand::MOLoad);
27552755
}
27562756

‎llvm/lib/Target/X86/X86ISelDAGToDAG.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1185,7 +1185,7 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
11851185
SDVTList VTs = CurDAG->getVTList(MVT::Other);
11861186
SDValue Ops[] = {N->getOperand(0), N->getOperand(1), MemTmp};
11871187
Store = CurDAG->getMemIntrinsicNode(X86ISD::FST, dl, VTs, Ops, MemVT,
1188-
MPI, /*Align*/ 0,
1188+
MPI, /*Align*/ None,
11891189
MachineMemOperand::MOStore);
11901190
if (N->getFlags().hasNoFPExcept()) {
11911191
SDNodeFlags Flags = Store->getFlags();
@@ -1201,9 +1201,9 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
12011201
if (!DstIsSSE) {
12021202
SDVTList VTs = CurDAG->getVTList(DstVT, MVT::Other);
12031203
SDValue Ops[] = {Store, MemTmp};
1204-
Result =
1205-
CurDAG->getMemIntrinsicNode(X86ISD::FLD, dl, VTs, Ops, MemVT, MPI,
1206-
/*Align*/ 0, MachineMemOperand::MOLoad);
1204+
Result = CurDAG->getMemIntrinsicNode(
1205+
X86ISD::FLD, dl, VTs, Ops, MemVT, MPI,
1206+
/*Align*/ None, MachineMemOperand::MOLoad);
12071207
if (N->getFlags().hasNoFPExcept()) {
12081208
SDNodeFlags Flags = Result->getFlags();
12091209
Flags.setNoFPExcept(true);

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