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[AArch64] Remove wrong processor feature
`fmov dX, dY` is not a preferred instruction, in contrast to the documentation. Previously introduced by: #144152
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‎llvm/lib/Target/AArch64/AArch64Processors.td‎

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -318,7 +318,6 @@ def TuneAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7",
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FeatureFuseAES, FeatureFuseCryptoEOR,
319319
FeatureStorePairSuppress,
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FeatureZCRegMoveGPR64,
321-
FeatureZCRegMoveFPR64,
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FeatureZCZeroing,
323322
FeatureZCZeroingFPWorkaround]>;
324323

@@ -332,7 +331,6 @@ def TuneAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10",
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FeatureFuseCryptoEOR,
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FeatureStorePairSuppress,
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FeatureZCRegMoveGPR64,
335-
FeatureZCRegMoveFPR64,
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FeatureZCZeroing]>;
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def TuneAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11",
@@ -345,7 +343,6 @@ def TuneAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11",
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FeatureFuseCryptoEOR,
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FeatureStorePairSuppress,
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FeatureZCRegMoveGPR64,
348-
FeatureZCRegMoveFPR64,
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FeatureZCZeroing]>;
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def TuneAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12",
@@ -358,7 +355,6 @@ def TuneAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12",
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FeatureFuseCryptoEOR,
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FeatureStorePairSuppress,
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FeatureZCRegMoveGPR64,
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FeatureZCRegMoveFPR64,
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FeatureZCZeroing]>;
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def TuneAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13",
@@ -371,7 +367,6 @@ def TuneAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13",
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FeatureFuseCryptoEOR,
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FeatureStorePairSuppress,
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FeatureZCRegMoveGPR64,
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FeatureZCRegMoveFPR64,
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FeatureZCZeroing]>;
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def TuneAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14",
@@ -389,7 +384,6 @@ def TuneAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14",
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FeatureFuseLiterals,
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FeatureStorePairSuppress,
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FeatureZCRegMoveGPR64,
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FeatureZCRegMoveFPR64,
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FeatureZCZeroing]>;
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def TuneAppleA15 : SubtargetFeature<"apple-a15", "ARMProcFamily", "AppleA15",
@@ -407,7 +401,6 @@ def TuneAppleA15 : SubtargetFeature<"apple-a15", "ARMProcFamily", "AppleA15",
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FeatureFuseLiterals,
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FeatureStorePairSuppress,
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FeatureZCRegMoveGPR64,
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FeatureZCRegMoveFPR64,
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FeatureZCZeroing]>;
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def TuneAppleA16 : SubtargetFeature<"apple-a16", "ARMProcFamily", "AppleA16",
@@ -425,7 +418,6 @@ def TuneAppleA16 : SubtargetFeature<"apple-a16", "ARMProcFamily", "AppleA16",
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FeatureFuseLiterals,
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FeatureStorePairSuppress,
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FeatureZCRegMoveGPR64,
428-
FeatureZCRegMoveFPR64,
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FeatureZCZeroing]>;
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def TuneAppleA17 : SubtargetFeature<"apple-a17", "ARMProcFamily", "AppleA17",
@@ -443,7 +435,6 @@ def TuneAppleA17 : SubtargetFeature<"apple-a17", "ARMProcFamily", "AppleA17",
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FeatureFuseLiterals,
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FeatureStorePairSuppress,
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FeatureZCRegMoveGPR64,
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FeatureZCRegMoveFPR64,
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FeatureZCZeroing]>;
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def TuneAppleM4 : SubtargetFeature<"apple-m4", "ARMProcFamily", "AppleM4",
@@ -460,7 +451,6 @@ def TuneAppleM4 : SubtargetFeature<"apple-m4", "ARMProcFamily", "AppleM4",
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FeatureFuseCryptoEOR,
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FeatureFuseLiterals,
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FeatureZCRegMoveGPR64,
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FeatureZCRegMoveFPR64,
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FeatureZCZeroing
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]>;
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‎llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov-fpr.ll‎

Lines changed: 0 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,5 @@
11
; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s -check-prefixes=NOTCPU-LINUX --match-full-lines
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; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s -check-prefixes=NOTCPU-APPLE --match-full-lines
3-
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=CPU --match-full-lines
4-
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-fpr64 | FileCheck %s -check-prefixes=NOTATTR --match-full-lines
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; RUN: llc < %s -mtriple=arm64-apple-macosx -mattr=+zcm-fpr64 | FileCheck %s -check-prefixes=ATTR --match-full-lines
64

75
define void @zero_cycle_regmov_FPR32(float %a, float %b, float %c, float %d) {
@@ -23,22 +21,6 @@ entry:
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; NOTCPU-APPLE: fmov s0, [[REG1]]
2422
; NOTCPU-APPLE: fmov s1, [[REG2]]
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26-
; CPU: fmov [[REG2:d[0-9]+]], d3
27-
; CPU: fmov [[REG1:d[0-9]+]], d2
28-
; CPU: fmov d0, d2
29-
; CPU: fmov d1, d3
30-
; CPU-NEXT: bl {{_?foo_float}}
31-
; CPU: fmov d0, [[REG1]]
32-
; CPU: fmov d1, [[REG2]]
33-
34-
; NOTATTR: fmov [[REG2:s[0-9]+]], s3
35-
; NOTATTR: fmov [[REG1:s[0-9]+]], s2
36-
; NOTATTR: fmov s0, s2
37-
; NOTATTR: fmov s1, s3
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; NOTATTR-NEXT: bl {{_?foo_float}}
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; NOTATTR: fmov s0, [[REG1]]
40-
; NOTATTR: fmov s1, [[REG2]]
41-
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; ATTR: fmov d0, d2
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; ATTR: fmov d1, d3
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; ATTR: fmov [[REG2:d[0-9]+]], d3
@@ -72,22 +54,6 @@ entry:
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; NOTCPU-APPLE: fmov s0, [[REG1]]
7355
; NOTCPU-APPLE: fmov s1, [[REG2]]
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; CPU: fmov [[REG2:d[0-9]+]], d3
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; CPU: fmov [[REG1:d[0-9]+]], d2
77-
; CPU: fmov d0, d2
78-
; CPU: fmov d1, d3
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; CPU-NEXT: bl {{_?foo_half}}
80-
; CPU: fmov d0, [[REG1]]
81-
; CPU: fmov d1, [[REG2]]
82-
83-
; NOTATTR: fmov [[REG2:s[0-9]+]], s3
84-
; NOTATTR: fmov [[REG1:s[0-9]+]], s2
85-
; NOTATTR: fmov s0, s2
86-
; NOTATTR: fmov s1, s3
87-
; NOTATTR-NEXT: bl {{_?foo_half}}
88-
; NOTATTR: fmov s0, [[REG1]]
89-
; NOTATTR: fmov s1, [[REG2]]
90-
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; ATTR: fmov d0, d2
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; ATTR: fmov d1, d3
9359
; ATTR: fmov [[REG2:d[0-9]+]], d3

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