[RISCV] Improve hasAllNBitUsers for users of SLLI.

We can increase the number of Bits passes to the users by adding
the shift amount.

Author: topperc

llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

@@ -215,11 +215,13 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
 
       // these overwrite higher input bits, otherwise the lower word of output
       // depends only on the lower word of input. So check their uses read W.
-      case RISCV::SLLI:
-        if (Bits >= (ST.getXLen() - UserMI->getOperand(2).getImm()))
+      case RISCV::SLLI: {
+        unsigned ShAmt = UserMI->getOperand(2).getImm();
+        if (Bits >= (ST.getXLen() - ShAmt))
           break;
-        Worklist.push_back(std::make_pair(UserMI, Bits));
+        Worklist.push_back(std::make_pair(UserMI, Bits + ShAmt));
         break;
+      }
       case RISCV::ANDI: {
         uint64_t Imm = UserMI->getOperand(2).getImm();
         if (Bits >= (unsigned)llvm::bit_width(Imm))

llvm/test/CodeGen/RISCV/imm.ll

@@ -896,7 +896,7 @@ define i64 @imm64_8() nounwind {
 ; RV64-NOPOOL-LABEL: imm64_8:
 ; RV64-NOPOOL:       # %bb.0:
 ; RV64-NOPOOL-NEXT:    lui a0, 583
-; RV64-NOPOOL-NEXT:    addiw a0, a0, -1875
+; RV64-NOPOOL-NEXT:    addi a0, a0, -1875
 ; RV64-NOPOOL-NEXT:    slli a0, a0, 14
 ; RV64-NOPOOL-NEXT:    addi a0, a0, -947
 ; RV64-NOPOOL-NEXT:    slli a0, a0, 12
@@ -925,7 +925,7 @@ define i64 @imm64_8() nounwind {
 ; RV64IZBB-LABEL: imm64_8:
 ; RV64IZBB:       # %bb.0:
 ; RV64IZBB-NEXT:    lui a0, 583
-; RV64IZBB-NEXT:    addiw a0, a0, -1875
+; RV64IZBB-NEXT:    addi a0, a0, -1875
 ; RV64IZBB-NEXT:    slli a0, a0, 14
 ; RV64IZBB-NEXT:    addi a0, a0, -947
 ; RV64IZBB-NEXT:    slli a0, a0, 12
@@ -937,7 +937,7 @@ define i64 @imm64_8() nounwind {
 ; RV64IZBS-LABEL: imm64_8:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 583
-; RV64IZBS-NEXT:    addiw a0, a0, -1875
+; RV64IZBS-NEXT:    addi a0, a0, -1875
 ; RV64IZBS-NEXT:    slli a0, a0, 14
 ; RV64IZBS-NEXT:    addi a0, a0, -947
 ; RV64IZBS-NEXT:    slli a0, a0, 12
@@ -949,7 +949,7 @@ define i64 @imm64_8() nounwind {
 ; RV64IXTHEADBB-LABEL: imm64_8:
 ; RV64IXTHEADBB:       # %bb.0:
 ; RV64IXTHEADBB-NEXT:    lui a0, 583
-; RV64IXTHEADBB-NEXT:    addiw a0, a0, -1875
+; RV64IXTHEADBB-NEXT:    addi a0, a0, -1875
 ; RV64IXTHEADBB-NEXT:    slli a0, a0, 14
 ; RV64IXTHEADBB-NEXT:    addi a0, a0, -947
 ; RV64IXTHEADBB-NEXT:    slli a0, a0, 12
@@ -969,7 +969,7 @@ define i64 @imm64_8() nounwind {
 ; RV64-REMAT-LABEL: imm64_8:
 ; RV64-REMAT:       # %bb.0:
 ; RV64-REMAT-NEXT:    lui a0, 583
-; RV64-REMAT-NEXT:    addiw a0, a0, -1875
+; RV64-REMAT-NEXT:    addi a0, a0, -1875
 ; RV64-REMAT-NEXT:    slli a0, a0, 14
 ; RV64-REMAT-NEXT:    addi a0, a0, -947
 ; RV64-REMAT-NEXT:    slli a0, a0, 12

llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll

@@ -582,7 +582,7 @@ define i64 @imm64_8() nounwind {
 ; RV64-NOPOOL-LABEL: imm64_8:
 ; RV64-NOPOOL:       # %bb.0:
 ; RV64-NOPOOL-NEXT:    lui a0, 583
-; RV64-NOPOOL-NEXT:    addiw a0, a0, -1875
+; RV64-NOPOOL-NEXT:    addi a0, a0, -1875
 ; RV64-NOPOOL-NEXT:    slli a0, a0, 14
 ; RV64-NOPOOL-NEXT:    addi a0, a0, -947
 ; RV64-NOPOOL-NEXT:    slli a0, a0, 12
@@ -611,7 +611,7 @@ define i64 @imm64_8() nounwind {
 ; RV64IZBB-LABEL: imm64_8:
 ; RV64IZBB:       # %bb.0:
 ; RV64IZBB-NEXT:    lui a0, 583
-; RV64IZBB-NEXT:    addiw a0, a0, -1875
+; RV64IZBB-NEXT:    addi a0, a0, -1875
 ; RV64IZBB-NEXT:    slli a0, a0, 14
 ; RV64IZBB-NEXT:    addi a0, a0, -947
 ; RV64IZBB-NEXT:    slli a0, a0, 12
@@ -623,7 +623,7 @@ define i64 @imm64_8() nounwind {
 ; RV64IZBS-LABEL: imm64_8:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 583
-; RV64IZBS-NEXT:    addiw a0, a0, -1875
+; RV64IZBS-NEXT:    addi a0, a0, -1875
 ; RV64IZBS-NEXT:    slli a0, a0, 14
 ; RV64IZBS-NEXT:    addi a0, a0, -947
 ; RV64IZBS-NEXT:    slli a0, a0, 12
@@ -635,7 +635,7 @@ define i64 @imm64_8() nounwind {
 ; RV64IXTHEADBB-LABEL: imm64_8:
 ; RV64IXTHEADBB:       # %bb.0:
 ; RV64IXTHEADBB-NEXT:    lui a0, 583
-; RV64IXTHEADBB-NEXT:    addiw a0, a0, -1875
+; RV64IXTHEADBB-NEXT:    addi a0, a0, -1875
 ; RV64IXTHEADBB-NEXT:    slli a0, a0, 14
 ; RV64IXTHEADBB-NEXT:    addi a0, a0, -947
 ; RV64IXTHEADBB-NEXT:    slli a0, a0, 12

llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll

@@ -140,7 +140,7 @@ define <512 x i8> @two_source(<512 x i8> %a, <512 x i8> %b) {
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m1, ta, ma
 ; CHECK-NEXT:    vmv.v.i v24, 0
 ; CHECK-NEXT:    lui a2, 1047552
-; CHECK-NEXT:    addiw a2, a2, 1
+; CHECK-NEXT:    addi a2, a2, 1
 ; CHECK-NEXT:    slli a2, a2, 23
 ; CHECK-NEXT:    addi a2, a2, 1
 ; CHECK-NEXT:    slli a2, a2, 18