Mark speculative query methods as const

Change-Id: I9ebe0cf7252068dcee90d419945085efae75547d

Author: jrbyrnes

llvm/lib/Target/AMDGPU/GCNRegPressure.cpp

@@ -448,19 +448,6 @@ void GCNRPTracker::reset(const MachineRegisterInfo &MRI_,
   MaxPressure = CurPressure = getRegPressure(MRI_, LiveRegs_);
 }
 
-void GCNRPTracker::bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs) {
-  GCNRegPressure TempPressure = CurPressure;
-  for (const RegisterMaskPair &P : DeadDefs) {
-    Register Reg = P.RegUnit;
-    if (!Reg.isVirtual())
-      continue;
-    LaneBitmask LiveMask = LiveRegs[Reg];
-    LaneBitmask BumpedMask = LiveMask | P.LaneMask;
-    CurPressure.inc(Reg, LiveMask, BumpedMask, *MRI);
-  }
-  MaxPressure = max(MaxPressure, CurPressure);
-  CurPressure = TempPressure;
-}
 /// Mostly copy/paste from CodeGen/RegisterPressure.cpp
 LaneBitmask GCNRPTracker::getLastUsedLanes(Register RegUnit,
                                            SlotIndex Pos) const {
@@ -535,8 +522,9 @@ void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
   assert(CurPressure == getRegPressure(*MRI, LiveRegs));
 }
 
-void GCNUpwardRPTracker::bumpUpwardPressure(const MachineInstr *MI,
-                                            const SIRegisterInfo *TRI) {
+GCNRegPressure
+GCNUpwardRPTracker::bumpUpwardPressure(const MachineInstr *MI,
+                                       const SIRegisterInfo *TRI) const {
   assert(!MI->isDebugOrPseudoInstr() && "Expect a nondebug instruction.");
 
   SlotIndex SlotIdx = LIS.getInstructionIndex(*MI).getRegSlot();
@@ -549,33 +537,32 @@ void GCNUpwardRPTracker::bumpUpwardPressure(const MachineInstr *MI,
   adjustDefLaneLiveness(RegOpers.Defs, SlotIdx, LIS, *MRI);
   RegOpers.detectDeadDefs(*MI, LIS);
 
-  // Boost max pressure for all dead defs together.
-  // Since CurrSetPressure and MaxSetPressure
-  bumpDeadDefs(RegOpers.DeadDefs);
+  GCNRegPressure TempPressure = CurPressure;
 
   // Kill liveness at live defs.
   for (const RegisterMaskPair &P : RegOpers.Defs) {
     Register Reg = P.RegUnit;
     if (!Reg.isVirtual())
       continue;
-    LaneBitmask LiveAfter = LiveRegs[Reg];
+    LaneBitmask LiveAfter =
+        LiveRegs.contains(Reg) ? LiveRegs.at(Reg) : LaneBitmask(0);
     LaneBitmask UseLanes = getRegLanes(RegOpers.Uses, Reg);
     LaneBitmask DefLanes = P.LaneMask;
     LaneBitmask LiveBefore = (LiveAfter & ~DefLanes) | UseLanes;
 
-    CurPressure.inc(Reg, LiveAfter, LiveAfter & LiveBefore, *MRI);
-    MaxPressure = max(MaxPressure, CurPressure);
+    TempPressure.inc(Reg, LiveAfter, LiveAfter & LiveBefore, *MRI);
   }
   // Generate liveness for uses.
   for (const RegisterMaskPair &P : RegOpers.Uses) {
     Register Reg = P.RegUnit;
     if (!Reg.isVirtual())
       continue;
-    LaneBitmask LiveAfter = LiveRegs[Reg];
+    LaneBitmask LiveAfter =
+        LiveRegs.contains(Reg) ? LiveRegs.at(Reg) : LaneBitmask(0);
     LaneBitmask LiveBefore = LiveAfter | P.LaneMask;
-    CurPressure.inc(Reg, LiveAfter, LiveBefore, *MRI);
+    TempPressure.inc(Reg, LiveAfter, LiveBefore, *MRI);
   }
-  MaxPressure = max(MaxPressure, CurPressure);
+  return TempPressure;
 }
 
 ////////////////////////////////////////////////////////////////////////////////
@@ -736,8 +723,9 @@ Printable llvm::reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
   });
 }
 
-void GCNDownwardRPTracker::bumpDownwardPressure(const MachineInstr *MI,
-                                                const SIRegisterInfo *TRI) {
+GCNRegPressure
+GCNDownwardRPTracker::bumpDownwardPressure(const MachineInstr *MI,
+                                           const SIRegisterInfo *TRI) const {
   assert(!MI->isDebugOrPseudoInstr() && "Expect a nondebug instruction.");
 
   SlotIndex SlotIdx;
@@ -747,6 +735,7 @@ void GCNDownwardRPTracker::bumpDownwardPressure(const MachineInstr *MI,
   RegisterOperands RegOpers;
   RegOpers.collect(*MI, *TRI, *MRI, true, /*IgnoreDead=*/false);
   RegOpers.adjustLaneLiveness(LIS, *MRI, SlotIdx);
+  GCNRegPressure TempPressure = CurPressure;
 
   for (const RegisterMaskPair &Use : RegOpers.Uses) {
     Register Reg = Use.RegUnit;
@@ -775,24 +764,24 @@ void GCNDownwardRPTracker::bumpDownwardPressure(const MachineInstr *MI,
     if (LastUseMask.none())
       continue;
 
-    LaneBitmask LiveMask = LiveRegs[Reg];
+    LaneBitmask LiveMask =
+        LiveRegs.contains(Reg) ? LiveRegs.at(Reg) : LaneBitmask(0);
     LaneBitmask NewMask = LiveMask & ~LastUseMask;
-    CurPressure.inc(Reg, LiveMask, NewMask, *MRI);
+    TempPressure.inc(Reg, LiveMask, NewMask, *MRI);
   }
 
   // Generate liveness for defs.
   for (const RegisterMaskPair &Def : RegOpers.Defs) {
     Register Reg = Def.RegUnit;
     if (!Reg.isVirtual())
       continue;
-    LaneBitmask LiveMask = LiveRegs[Reg];
+    LaneBitmask LiveMask =
+        LiveRegs.contains(Reg) ? LiveRegs.at(Reg) : LaneBitmask(0);
     LaneBitmask NewMask = LiveMask | Def.LaneMask;
-    CurPressure.inc(Reg, LiveMask, NewMask, *MRI);
+    TempPressure.inc(Reg, LiveMask, NewMask, *MRI);
   }
-  MaxPressure = max(MaxPressure, CurPressure);
 
-  // Boost pressure for all dead defs together.
-  bumpDeadDefs(RegOpers.DeadDefs);
+  return TempPressure;
 }
 
 bool GCNUpwardRPTracker::isValid() const {

llvm/lib/Target/AMDGPU/GCNRegPressure.h

@@ -228,7 +228,8 @@ class GCNUpwardRPTracker : public GCNRPTracker {
   /// does not rely on the implicit program ordering in the LiveIntervals to
   /// support RP Speculation. It leaves the state of pressure inconsistent with
   /// the current position
-  void bumpUpwardPressure(const MachineInstr *MI, const SIRegisterInfo *TRI);
+  GCNRegPressure bumpUpwardPressure(const MachineInstr *MI,
+                                    const SIRegisterInfo *TRI) const;
 
   /// \p returns whether the tracker's state after receding MI corresponds
   /// to reported by LIS.
@@ -315,7 +316,8 @@ class GCNDownwardRPTracker : public GCNRPTracker {
   /// does not rely on the implicit program ordering in the LiveIntervals to
   /// support RP Speculation. It leaves the state of pressure inconsistent with
   /// the current position
-  void bumpDownwardPressure(const MachineInstr *MI, const SIRegisterInfo *TRI);
+  GCNRegPressure bumpDownwardPressure(const MachineInstr *MI,
+                                      const SIRegisterInfo *TRI) const;
 };
 
 LaneBitmask getLiveLaneMask(unsigned Reg,

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

@@ -173,25 +173,18 @@ static void getRegisterPressures(
   // GCNTrackers
   Pressure.resize(4, 0);
   MachineInstr *MI = SU->getInstr();
+  GCNRegPressure NewPressure;
   if (AtTop) {
     GCNDownwardRPTracker TempDownwardTracker(DownwardTracker);
-    TempDownwardTracker.bumpDownwardPressure(MI, SRI);
-    Pressure[AMDGPU::RegisterPressureSets::SReg_32] =
-        TempDownwardTracker.getPressure().getSGPRNum();
-    Pressure[AMDGPU::RegisterPressureSets::VGPR_32] =
-        TempDownwardTracker.getPressure().getArchVGPRNum();
-    Pressure[AMDGPU::RegisterPressureSets::AGPR_32] =
-        TempDownwardTracker.getPressure().getAGPRNum();
+    NewPressure = TempDownwardTracker.bumpDownwardPressure(MI, SRI);
   } else {
     GCNUpwardRPTracker TempUpwardTracker(UpwardTracker);
-    TempUpwardTracker.bumpUpwardPressure(MI, SRI);
-    Pressure[AMDGPU::RegisterPressureSets::SReg_32] =
-        TempUpwardTracker.getPressure().getSGPRNum();
-    Pressure[AMDGPU::RegisterPressureSets::VGPR_32] =
-        TempUpwardTracker.getPressure().getArchVGPRNum();
-    Pressure[AMDGPU::RegisterPressureSets::AGPR_32] =
-        TempUpwardTracker.getPressure().getAGPRNum();
+    NewPressure = TempUpwardTracker.bumpUpwardPressure(MI, SRI);
   }
+  Pressure[AMDGPU::RegisterPressureSets::SReg_32] = NewPressure.getSGPRNum();
+  Pressure[AMDGPU::RegisterPressureSets::VGPR_32] =
+      NewPressure.getArchVGPRNum();
+  Pressure[AMDGPU::RegisterPressureSets::AGPR_32] = NewPressure.getAGPRNum();
 }
 
 void GCNSchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU,