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Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
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‎clang/docs/ReleaseNotes.rst‎

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@@ -216,6 +216,8 @@ X86 Support
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functions defined by the ``*mmintrin.h`` headers. A mapping can be
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found in the file ``clang/www/builtins.py``.
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- Support ISA of ``AVX10.2``.
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Arm and AArch64 Support
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^^^^^^^^^^^^^^^^^^^^^^^
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‎clang/include/clang/Basic/BuiltinsX86.def‎

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@@ -1959,6 +1959,14 @@ TARGET_HEADER_BUILTIN(__readgsword, "UsUNi", "nh", INTRIN_H, ALL_MS_LANGUAGES,
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TARGET_HEADER_BUILTIN(__readgsdword, "UNiUNi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
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TARGET_HEADER_BUILTIN(__readgsqword, "ULLiUNi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
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// AVX10.2 VMPSADBW
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TARGET_BUILTIN(__builtin_ia32_mpsadbw512, "V32sV64cV64cIc", "ncV:512:", "avx10.2-512")
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// AVX10.2 YMM Rounding
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TARGET_BUILTIN(__builtin_ia32_vaddpd256_round, "V4dV4dV4dIi", "nV:256:", "avx10.2-256")
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TARGET_BUILTIN(__builtin_ia32_vaddph256_round, "V16xV16xV16xIi", "nV:256:", "avx10.2-256")
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TARGET_BUILTIN(__builtin_ia32_vaddps256_round, "V8fV8fV8fIi", "nV:256:", "avx10.2-256")
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// AVX-VNNI-INT16
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TARGET_BUILTIN(__builtin_ia32_vpdpwsud128, "V4iV4iV4iV4i", "nV:128:", "avxvnniint16")
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TARGET_BUILTIN(__builtin_ia32_vpdpwsud256, "V8iV8iV8iV8i", "nV:256:", "avxvnniint16")

‎clang/include/clang/Driver/Options.td‎

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@@ -6205,6 +6205,12 @@ def mavx10_1_512 : Flag<["-"], "mavx10.1-512">, Group<m_x86_AVX10_Features_Group
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def mno_avx10_1_512 : Flag<["-"], "mno-avx10.1-512">, Group<m_x86_AVX10_Features_Group>;
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def mavx10_1 : Flag<["-"], "mavx10.1">, Alias<mavx10_1_256>;
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def mno_avx10_1 : Flag<["-"], "mno-avx10.1">, Alias<mno_avx10_1_256>;
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def mavx10_2_256 : Flag<["-"], "mavx10.2-256">, Group<m_x86_AVX10_Features_Group>;
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def mno_avx10_2_256 : Flag<["-"], "mno-avx10.2-256">, Group<m_x86_AVX10_Features_Group>;
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def mavx10_2_512 : Flag<["-"], "mavx10.2-512">, Group<m_x86_AVX10_Features_Group>;
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def mno_avx10_2_512 : Flag<["-"], "mno-avx10.2-512">, Group<m_x86_AVX10_Features_Group>;
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def mavx10_2 : Flag<["-"], "mavx10.2">, Alias<mavx10_2_256>;
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def mno_avx10_2 : Flag<["-"], "mno-avx10.2">, Alias<mno_avx10_2_256>;
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def mavx2 : Flag<["-"], "mavx2">, Group<m_x86_Features_Group>;
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def mno_avx2 : Flag<["-"], "mno-avx2">, Group<m_x86_Features_Group>;
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def mavx512f : Flag<["-"], "mavx512f">, Group<m_x86_Features_Group>;

‎clang/lib/Basic/Targets/X86.cpp‎

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@@ -304,6 +304,10 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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HasAVX10_1 = true;
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} else if (Feature == "+avx10.1-512") {
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HasAVX10_1_512 = true;
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} else if (Feature == "+avx10.2-256") {
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HasAVX10_2 = true;
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} else if (Feature == "+avx10.2-512") {
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HasAVX10_2_512 = true;
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} else if (Feature == "+avx512cd") {
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HasAVX512CD = true;
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} else if (Feature == "+avx512vpopcntdq") {
@@ -824,6 +828,10 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
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Builder.defineMacro("__AVX10_1__");
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if (HasAVX10_1_512)
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Builder.defineMacro("__AVX10_1_512__");
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if (HasAVX10_2)
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Builder.defineMacro("__AVX10_2__");
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if (HasAVX10_2_512)
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Builder.defineMacro("__AVX10_2_512__");
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if (HasAVX512CD)
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Builder.defineMacro("__AVX512CD__");
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if (HasAVX512VPOPCNTDQ)
@@ -1056,6 +1064,8 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
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.Case("avx", true)
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.Case("avx10.1-256", true)
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.Case("avx10.1-512", true)
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.Case("avx10.2-256", true)
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.Case("avx10.2-512", true)
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.Case("avx2", true)
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.Case("avx512f", true)
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.Case("avx512cd", true)
@@ -1171,6 +1181,8 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
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.Case("avx", SSELevel >= AVX)
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.Case("avx10.1-256", HasAVX10_1)
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.Case("avx10.1-512", HasAVX10_1_512)
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.Case("avx10.2-256", HasAVX10_2)
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.Case("avx10.2-512", HasAVX10_2_512)
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.Case("avx2", SSELevel >= AVX2)
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.Case("avx512f", SSELevel >= AVX512F)
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.Case("avx512cd", HasAVX512CD)

‎clang/lib/Basic/Targets/X86.h‎

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@@ -92,6 +92,8 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
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bool HasF16C = false;
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bool HasAVX10_1 = false;
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bool HasAVX10_1_512 = false;
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bool HasAVX10_2 = false;
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bool HasAVX10_2_512 = false;
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bool HasEVEX512 = false;
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bool HasAVX512CD = false;
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bool HasAVX512VPOPCNTDQ = false;

‎clang/lib/Driver/ToolChains/Arch/X86.cpp‎

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@@ -241,7 +241,7 @@ void x86::getX86TargetFeatures(const Driver &D, const llvm::Triple &Triple,
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assert(Name.starts_with("avx10.") && "Invalid AVX10 feature name.");
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StringRef Version, Width;
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std::tie(Version, Width) = Name.substr(6).split('-');
244-
assert(Version == "1" && "Invalid AVX10 feature name.");
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assert((Version == "1" || Version == "2") && "Invalid AVX10 feature name.");
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assert((Width == "256" || Width == "512") && "Invalid AVX10 feature name.");
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#endif
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‎clang/lib/Headers/CMakeLists.txt‎

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@@ -147,6 +147,8 @@ set(x86_files
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amxcomplexintrin.h
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amxfp16intrin.h
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amxintrin.h
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avx10_2_512niintrin.h
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avx10_2niintrin.h
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avx2intrin.h
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avx512bf16intrin.h
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avx512bitalgintrin.h

‎clang/lib/Headers/avx10_2_512niintrin.h‎

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@@ -0,0 +1,35 @@
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/*===---- avx10_2_512niintrin.h - AVX10.2-512 new instruction intrinsics ---===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
*
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*===-----------------------------------------------------------------------===
8+
*/
9+
#ifndef __IMMINTRIN_H
10+
#error \
11+
"Never use <avx10_2_512niintrin.h> directly; include <immintrin.h> instead."
12+
#endif
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14+
#ifdef __SSE2__
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16+
#ifndef __AVX10_2_512INTRIN_H
17+
#define __AVX10_2_512INTRIN_H
18+
19+
/* VMPSADBW */
20+
#define _mm512_mpsadbw_epu8(A, B, imm) \
21+
((__m512i)__builtin_ia32_mpsadbw512((__v64qi)(__m512i)(A), \
22+
(__v64qi)(__m512i)(B), (int)(imm)))
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24+
#define _mm512_mask_mpsadbw_epu8(W, U, A, B, imm) \
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((__m512i)__builtin_ia32_selectw_512( \
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(__mmask32)(U), (__v32hi)_mm512_mpsadbw_epu8((A), (B), (imm)), \
27+
(__v32hi)(__m512i)(W)))
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29+
#define _mm512_maskz_mpsadbw_epu8(U, A, B, imm) \
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((__m512i)__builtin_ia32_selectw_512( \
31+
(__mmask32)(U), (__v32hi)_mm512_mpsadbw_epu8((A), (B), (imm)), \
32+
(__v32hi)_mm512_setzero_si512()))
33+
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#endif /* __SSE2__ */
35+
#endif /* __AVX10_2_512INTRIN_H */

‎clang/lib/Headers/avx10_2niintrin.h‎

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@@ -0,0 +1,83 @@
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/*===---- avx10_2niintrin.h - AVX10.2 new instruction intrinsics -----------===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
* See https://llvm.org/LICENSE.txt for license information.
5+
* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
*
7+
*===-----------------------------------------------------------------------===
8+
*/
9+
#ifndef __IMMINTRIN_H
10+
#error "Never use <avx10_2niintrin.h> directly; include <immintrin.h> instead."
11+
#endif
12+
13+
#ifdef __SSE2__
14+
15+
#ifndef __AVX10_2INTRIN_H
16+
#define __AVX10_2INTRIN_H
17+
18+
/* VMPSADBW */
19+
#define _mm_mask_mpsadbw_epu8(W, U, A, B, imm) \
20+
((__m128i)__builtin_ia32_selectw_128( \
21+
(__mmask8)(U), (__v8hi)_mm_mpsadbw_epu8((A), (B), (imm)), \
22+
(__v8hi)(__m128i)(W)))
23+
24+
#define _mm_maskz_mpsadbw_epu8(U, A, B, imm) \
25+
((__m128i)__builtin_ia32_selectw_128( \
26+
(__mmask8)(U), (__v8hi)_mm_mpsadbw_epu8((A), (B), (imm)), \
27+
(__v8hi)_mm_setzero_si128()))
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29+
#define _mm256_mask_mpsadbw_epu8(W, U, A, B, imm) \
30+
((__m256i)__builtin_ia32_selectw_256( \
31+
(__mmask16)(U), (__v16hi)_mm256_mpsadbw_epu8((A), (B), (imm)), \
32+
(__v16hi)(__m256i)(W)))
33+
34+
#define _mm256_maskz_mpsadbw_epu8(U, A, B, imm) \
35+
((__m256i)__builtin_ia32_selectw_256( \
36+
(__mmask16)(U), (__v16hi)_mm256_mpsadbw_epu8((A), (B), (imm)), \
37+
(__v16hi)_mm256_setzero_si256()))
38+
39+
/* YMM Rounding */
40+
#define _mm256_add_round_pd(A, B, R) \
41+
((__m256d)__builtin_ia32_vaddpd256_round((__v4df)(__m256d)(A), \
42+
(__v4df)(__m256d)(B), (int)(R)))
43+
44+
#define _mm256_mask_add_round_pd(W, U, A, B, R) \
45+
((__m256d)__builtin_ia32_selectpd_256( \
46+
(__mmask8)(U), (__v4df)_mm256_add_round_pd((A), (B), (R)), \
47+
(__v4df)(__m256d)(W)))
48+
49+
#define _mm256_maskz_add_round_pd(U, A, B, R) \
50+
((__m256d)__builtin_ia32_selectpd_256( \
51+
(__mmask8)(U), (__v4df)_mm256_add_round_pd((A), (B), (R)), \
52+
(__v4df)_mm256_setzero_pd()))
53+
54+
#define _mm256_add_round_ph(A, B, R) \
55+
((__m256h)__builtin_ia32_vaddph256_round((__v16hf)(__m256h)(A), \
56+
(__v16hf)(__m256h)(B), (int)(R)))
57+
58+
#define _mm256_mask_add_round_ph(W, U, A, B, R) \
59+
((__m256h)__builtin_ia32_selectph_256( \
60+
(__mmask16)(U), (__v16hf)_mm256_add_round_ph((A), (B), (R)), \
61+
(__v16hf)(__m256h)(W)))
62+
63+
#define _mm256_maskz_add_round_ph(U, A, B, R) \
64+
((__m256h)__builtin_ia32_selectph_256( \
65+
(__mmask16)(U), (__v16hf)_mm256_add_round_ph((A), (B), (R)), \
66+
(__v16hf)_mm256_setzero_ph()))
67+
68+
#define _mm256_add_round_ps(A, B, R) \
69+
((__m256)__builtin_ia32_vaddps256_round((__v8sf)(__m256)(A), \
70+
(__v8sf)(__m256)(B), (int)(R)))
71+
72+
#define _mm256_mask_add_round_ps(W, U, A, B, R) \
73+
((__m256)__builtin_ia32_selectps_256( \
74+
(__mmask8)(U), (__v8sf)_mm256_add_round_ps((A), (B), (R)), \
75+
(__v8sf)(__m256)(W)))
76+
77+
#define _mm256_maskz_add_round_ps(U, A, B, R) \
78+
((__m256)__builtin_ia32_selectps_256( \
79+
(__mmask8)(U), (__v8sf)_mm256_add_round_ps((A), (B), (R)), \
80+
(__v8sf)_mm256_setzero_ps()))
81+
82+
#endif /* __AVX10_2INTRIN_H */
83+
#endif /* __SSE2__ */

‎clang/lib/Headers/immintrin.h‎

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@@ -648,6 +648,14 @@ _storebe_i64(void * __P, long long __D) {
648648
#include <avx512vlvp2intersectintrin.h>
649649
#endif
650650

651+
#if !defined(__SCE__) || __has_feature(modules) || defined(__AVX10_2__)
652+
#include <avx10_2niintrin.h>
653+
#endif
654+
655+
#if !defined(__SCE__) || __has_feature(modules) || defined(__AVX10_2_512__)
656+
#include <avx10_2_512niintrin.h>
657+
#endif
658+
651659
#if !defined(__SCE__) || __has_feature(modules) || defined(__ENQCMD__)
652660
#include <enqcmdintrin.h>
653661
#endif

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