[PowerPC] Define SchedModel for Power8

PowerPC subtargets prior to Power9 use the 'legacy' itinerary way to
provide scheduling information. This patch re-writes the tablegen file
to define the scheduling information in the new SchedModel way, which
can bring improvements to some benchmarks.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D154488

Author: ecnelises

llvm/lib/Target/PowerPC/PPCScheduleP8.td

@@ -9,14 +9,14 @@ define i32 @test(i32 %i) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 4, 2, .LC0@toc@ha
 ; CHECK-NEXT:    extsw 3, 3
-; CHECK-NEXT:    addis 5, 2, .LC1@toc@ha
 ; CHECK-NEXT:    ld 4, .LC0@toc@l(4)
 ; CHECK-NEXT:    ld 4, 0(4)
 ; CHECK-NEXT:    lbzx 3, 4, 3
-; CHECK-NEXT:    ld 4, .LC1@toc@l(5)
+; CHECK-NEXT:    addis 4, 2, .LC1@toc@ha
+; CHECK-NEXT:    ld 4, .LC1@toc@l(4)
 ; CHECK-NEXT:    subfic 3, 3, 1
-; CHECK-NEXT:    ld 4, 0(4)
 ; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    ld 4, 0(4)
 ; CHECK-NEXT:    sldi 3, 3, 2
 ; CHECK-NEXT:    lwzx 3, 4, 3
 ; CHECK-NEXT:    blr

llvm/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll

@@ -202,58 +202,52 @@ define void @_ZN5clang6format22BreakableStringLiteral11insertBreakEjjSt4pairImjE
 ; CHECK-LABEL: _ZN5clang6format22BreakableStringLiteral11insertBreakEjjSt4pairImjERNS0_17WhitespaceManagerE:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ld 10, 56(3)
-; CHECK-NEXT:    lwz 0, 40(3)
+; CHECK-NEXT:    lwz 4, 40(3)
 ; CHECK-NEXT:    mr 12, 8
 ; CHECK-NEXT:    cmpldi 10, 0
 ; CHECK-NEXT:    beq 0, .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %if.end.i.i
 ; CHECK-NEXT:    ld 9, 48(3)
-; CHECK-NEXT:    lbz 4, 0(9)
-; CHECK-NEXT:    cmpwi 4, 64
+; CHECK-NEXT:    lbz 8, 0(9)
+; CHECK-NEXT:    cmpwi 8, 64
 ; CHECK-NEXT:    b .LBB0_3
 ; CHECK-NEXT:  .LBB0_2: # %entry._ZNK4llvm9StringRef10startswithES0_.exit_crit_edge
 ; CHECK-NEXT:    ld 9, 48(3)
 ; CHECK-NEXT:    crxor 2, 2, 2
 ; CHECK-NEXT:  .LBB0_3: # %_ZNK4llvm9StringRef10startswithES0_.exit
-; CHECK-NEXT:    mflr 4
-; CHECK-NEXT:    .cfi_def_cfa_offset 160
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    .cfi_def_cfa_offset 144
 ; CHECK-NEXT:    .cfi_offset lr, 16
-; CHECK-NEXT:    .cfi_offset r28, -32
-; CHECK-NEXT:    .cfi_offset r29, -24
 ; CHECK-NEXT:    .cfi_offset r30, -16
-; CHECK-NEXT:    std 28, -32(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 29, -24(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 30, -16(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stdu 1, -160(1)
-; CHECK-NEXT:    std 4, 176(1)
+; CHECK-NEXT:    stdu 1, -144(1)
 ; CHECK-NEXT:    li 8, 0
 ; CHECK-NEXT:    li 11, 1
+; CHECK-NEXT:    std 0, 160(1)
 ; CHECK-NEXT:    add 5, 6, 5
-; CHECK-NEXT:    iseleq 30, 11, 8
+; CHECK-NEXT:    lbz 30, 20(3)
+; CHECK-NEXT:    clrldi 6, 7, 32
+; CHECK-NEXT:    iseleq 8, 11, 8
 ; CHECK-NEXT:    ld 11, 64(3)
-; CHECK-NEXT:    lbz 29, 20(3)
-; CHECK-NEXT:    lwz 28, 16(3)
 ; CHECK-NEXT:    add 5, 5, 10
+; CHECK-NEXT:    clrldi 5, 5, 32
+; CHECK-NEXT:    mr 7, 11
+; CHECK-NEXT:    sub 0, 4, 8
 ; CHECK-NEXT:    ld 4, 8(3)
 ; CHECK-NEXT:    ld 8, 72(3)
-; CHECK-NEXT:    sub 3, 0, 30
-; CHECK-NEXT:    clrldi 5, 5, 32
-; CHECK-NEXT:    li 0, 1
-; CHECK-NEXT:    clrldi 6, 7, 32
-; CHECK-NEXT:    extsw 30, 3
+; CHECK-NEXT:    lwz 3, 16(3)
+; CHECK-NEXT:    std 30, 96(1)
+; CHECK-NEXT:    extsw 0, 0
+; CHECK-NEXT:    std 3, 112(1)
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    std 0, 120(1)
+; CHECK-NEXT:    std 3, 104(1)
 ; CHECK-NEXT:    mr 3, 12
-; CHECK-NEXT:    mr 7, 11
-; CHECK-NEXT:    std 0, 104(1)
-; CHECK-NEXT:    std 28, 112(1)
-; CHECK-NEXT:    std 29, 96(1)
-; CHECK-NEXT:    std 30, 120(1)
 ; CHECK-NEXT:    bl _ZN5clang6format17WhitespaceManager24replaceWhitespaceInTokenERKNS0_11FormatTokenEjjN4llvm9StringRefES6_bjji
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    addi 1, 1, 160
+; CHECK-NEXT:    addi 1, 1, 144
 ; CHECK-NEXT:    ld 0, 16(1)
 ; CHECK-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 29, -24(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 28, -32(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 entry:

llvm/test/CodeGen/PowerPC/BreakableToken-reduced.ll

@@ -21,8 +21,8 @@ define dso_local signext i32 @caller1(i32 signext %a, i32 signext %b) local_unna
 ; CHECK-PWR8-NEXT:    #APP
 ; CHECK-PWR8-NEXT:    add r3, r3, r4
 ; CHECK-PWR8-NEXT:    #NO_APP
-; CHECK-PWR8-NEXT:    std r0, 192(r1)
 ; CHECK-PWR8-NEXT:    extsw r3, r3
+; CHECK-PWR8-NEXT:    std r0, 192(r1)
 ; CHECK-PWR8-NEXT:    bl callee
 ; CHECK-PWR8-NEXT:    nop
 ; CHECK-PWR8-NEXT:    addi r1, r1, 176
@@ -75,8 +75,8 @@ define dso_local signext i32 @caller2(i32 signext %a, i32 signext %b) local_unna
 ; CHECK-PWR8-NEXT:    #APP
 ; CHECK-PWR8-NEXT:    add r3, r3, r4
 ; CHECK-PWR8-NEXT:    #NO_APP
-; CHECK-PWR8-NEXT:    std r0, 192(r1)
 ; CHECK-PWR8-NEXT:    extsw r3, r3
+; CHECK-PWR8-NEXT:    std r0, 192(r1)
 ; CHECK-PWR8-NEXT:    bl callee
 ; CHECK-PWR8-NEXT:    nop
 ; CHECK-PWR8-NEXT:    addi r1, r1, 176

llvm/test/CodeGen/PowerPC/CSR-fit.ll

@@ -42,10 +42,10 @@ entry:
 ; CHECK: extsw r3,
 ; CHECK: bl call
 ; CHECK: sub r3,
-; CHECK: rldicl r3, r3, 1, 63
 ; CHECK: std r3, [[OFF:[0-9]+]](r1)
 ; CHECK: #APP
 ; CHECK: ld r3, [[OFF]](r1)
+; CHECK: rldicl r3, r3, 1, 63
 ; CHECK: xori r3, r3, 1
 ; CHECK: blr
 

llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll

@@ -22,15 +22,15 @@ define dso_local signext i32 @test_32byte_vector() nounwind {
 ; CHECK-LE-NEXT:    subfic r0, r0, -96
 ; CHECK-LE-NEXT:    stdux r1, r1, r0
 ; CHECK-LE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-LE-NEXT:    addis r4, r2, .LCPI0_1@toc@ha
 ; CHECK-LE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-LE-NEXT:    addi r4, r4, .LCPI0_1@toc@l
 ; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
-; CHECK-LE-NEXT:    lxvd2x vs1, 0, r4
-; CHECK-LE-NEXT:    addi r4, r1, 48
+; CHECK-LE-NEXT:    addi r3, r1, 48
+; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
+; CHECK-LE-NEXT:    addis r3, r2, .LCPI0_1@toc@ha
+; CHECK-LE-NEXT:    addi r3, r3, .LCPI0_1@toc@l
+; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-NEXT:    addi r3, r1, 32
-; CHECK-LE-NEXT:    stxvd2x vs0, 0, r4
-; CHECK-LE-NEXT:    stxvd2x vs1, 0, r3
+; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-LE-NEXT:    bl test
 ; CHECK-LE-NEXT:    nop
 ; CHECK-LE-NEXT:    lwa r3, 32(r1)
@@ -158,25 +158,24 @@ define dso_local void @test_Array() nounwind {
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mflr r0
 ; CHECK-LE-NEXT:    stdu r1, -176(r1)
-; CHECK-LE-NEXT:    addis r4, r2, Arr1@toc@ha
 ; CHECK-LE-NEXT:    li r3, 0
-; CHECK-LE-NEXT:    std r0, 192(r1)
+; CHECK-LE-NEXT:    addis r4, r2, Arr1@toc@ha
 ; CHECK-LE-NEXT:    li r6, 65
+; CHECK-LE-NEXT:    std r0, 192(r1)
 ; CHECK-LE-NEXT:    addi r5, r1, 46
-; CHECK-LE-NEXT:    addi r4, r4, Arr1@toc@l
 ; CHECK-LE-NEXT:    stw r3, 44(r1)
-; CHECK-LE-NEXT:    addi r4, r4, -1
+; CHECK-LE-NEXT:    addi r4, r4, Arr1@toc@l
 ; CHECK-LE-NEXT:    mtctr r6
+; CHECK-LE-NEXT:    addi r4, r4, -1
 ; CHECK-LE-NEXT:    bdz .LBB2_2
 ; CHECK-LE-NEXT:    .p2align 5
 ; CHECK-LE-NEXT:  .LBB2_1: # %for.body
 ; CHECK-LE-NEXT:    #
 ; CHECK-LE-NEXT:    lbz r6, 1(r4)
-; CHECK-LE-NEXT:    addi r7, r5, 2
 ; CHECK-LE-NEXT:    addi r4, r4, 1
 ; CHECK-LE-NEXT:    addi r3, r3, 1
 ; CHECK-LE-NEXT:    sth r6, 2(r5)
-; CHECK-LE-NEXT:    mr r5, r7
+; CHECK-LE-NEXT:    addi r5, r5, 2
 ; CHECK-LE-NEXT:    bdnz .LBB2_1
 ; CHECK-LE-NEXT:  .LBB2_2: # %for.cond.cleanup
 ; CHECK-LE-NEXT:    addi r3, r1, 48

llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll

@@ -19,8 +19,8 @@ define signext i32 @main() nounwind {
 ; CHECK-NEXT:    addi 6, 1, 46
 ; CHECK-NEXT:    sth 3, 46(1)
 ; CHECK-NEXT:    lis 3, 0
-; CHECK-NEXT:    ori 3, 3, 33059
 ; CHECK-NEXT:    sync
+; CHECK-NEXT:    ori 3, 3, 33059
 ; CHECK-NEXT:  .LBB0_1: # %L.entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lharx 5, 0, 6

llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll

@@ -15,7 +15,6 @@ define void @testExpandPostRAPseudo(ptr nocapture readonly %ptr) {
 ; CHECK-P8:    ld r4, .LC0@toc@l(r4)
 ; CHECK-P8:    xxspltw vs0, vs0, 1
 ; CHECK-P8;    stxvd2x vs0, 0, r4
-; CHECK-P8:    lis r4, 1024
 ; CHECK-P8:    lfiwax f0, 0, r3
 ; CHECK-P8:    addis r3, r2, .LC1@toc@ha
 ; CHECK-P8:    ld r3, .LC1@toc@l(r3)

llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll

@@ -86,12 +86,12 @@ entry:
 ; EXTABI:         bb.0.entry:
 ; EXTABI:         liveins: $f1, $x4
 ; EXTABI-DAG:     renamable $f0 = LFD 0, renamable $x4 :: (volatile load (s64) from %ir.b, align 4)
-; EXTABI-DAG:     renamable $f0 = nofpexcept XSADDDP killed renamable $f0, renamable $f1, implicit $rm
-; EXTABI-DAG:     renamable $vf31 = nofpexcept XSMULDP killed renamable $f1, renamable $f1, implicit $rm
+; EXTABI-DAG:     renamable $f0 = nofpexcept XSADDDP killed renamable $f0, $f1, implicit $rm
 ; EXTABI:         STFD killed renamable $f0, 0, renamable $x4 :: (volatile store (s64) into %ir.b, align 4)
 ; EXTABI-LABEL:   INLINEASM
-; EXTABI-DAG:     renamable $f0 = LFD 0, renamable $x4 :: (volatile load (s64) from %ir.b, align 4)
-; EXTABI-DAG:     renamable $f0 = nofpexcept XSADDDP killed renamable $vf31, killed renamable $f0, implicit $rm
+; EXTABI-DAG:     renamable $f0 = nofpexcept XSMULDP killed renamable $vf31, renamable $vf31, implicit $rm
+; EXTABI-DAG:     renamable $f1 = LFD 0, renamable $x4 :: (volatile load (s64) from %ir.b, align 4)
+; EXTABI-DAG:     renamable $f0 = nofpexcept XSADDDP killed renamable $f0, killed renamable $f1, implicit $rm
 ; EXTABI-DAG:     STFD killed renamable $f0, 0, renamable $x4 :: (volatile store (s64) into %ir.b, align 4)
 ; EXTABI:         renamable $f1 = LFD 0, killed renamable $x4 :: (volatile load (s64) from %ir.b, align 4)
 
@@ -144,12 +144,12 @@ entry:
 ; EXTABI:         body:             |
 ; EXTABI-DAG:     bb.0.entry:
 ; EXTABI-DAG:     liveins: $v2, $x3
-; EXTABI-DAG:     renamable $v3 = LXVW4X $zero8, renamable $x3 :: (volatile load (s128) from %ir.b, align 4)
 ; EXTABI-DAG:     renamable $v31 = COPY $v2
-; EXTABI-DAG:     renamable $v2 = VADDUWM killed renamable $v3, $v2
-; EXTABI-LABEL:   INLINEASM    
 ; EXTABI-DAG:     renamable $v2 = LXVW4X $zero8, renamable $x3 :: (volatile load (s128) from %ir.b, align 4)
-; EXTABI-DAG:     renamable $v3 = VMULUWM killed renamable $v31, renamable $v31
-; EXTABI-DAG:     renamable $v2 = VADDUWM killed renamable $v3, killed renamable $v2
+; EXTABI-DAG:     renamable $v2 = VADDUWM killed renamable $v2, renamable $v31
+; EXTABI-LABEL:   INLINEASM
+; EXTABI-DAG:     renamable $v2 = VMULUWM killed renamable $v31, renamable $v31
+; EXTABI-DAG:     renamable $v3 = LXVW4X $zero8, renamable $x3 :: (volatile load (s128) from %ir.b, align 4)
+; EXTABI-DAG:     renamable $v2 = VADDUWM killed renamable $v2, killed renamable $v3
 ; EXTABI-DAG:     STXVW4X killed renamable $v2, $zero8, renamable $x3 :: (volatile store (s128) into %ir.b, align 4)
 ; EXTABI:         renamable $v2 = LXVW4X $zero8, killed renamable $x3 :: (volatile load (s128) from %ir.b, align 4)

llvm/test/CodeGen/PowerPC/aix-dfltabi-rsrvd-reg.ll

@@ -36,20 +36,20 @@ define void @test_aix_splatimm(i32 %arg, i32 %arg1, i32 %arg2) {
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    bclr 12, 20, 0
 ; CHECK-NEXT:  # %bb.1: # %bb3
+; CHECK-NEXT:    slwi 3, 3, 8
 ; CHECK-NEXT:    srwi 4, 4, 16
+; CHECK-NEXT:    neg 3, 3
 ; CHECK-NEXT:    srwi 5, 5, 16
 ; CHECK-NEXT:    mullw 4, 5, 4
 ; CHECK-NEXT:    lwz 5, 0(3)
-; CHECK-NEXT:    slwi 3, 3, 8
-; CHECK-NEXT:    neg 3, 3
-; CHECK-NEXT:    srwi 5, 5, 1
 ; CHECK-NEXT:    mtvsrd 34, 3
 ; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    srwi 5, 5, 1
 ; CHECK-NEXT:    mullw 4, 4, 5
-; CHECK-NEXT:    vsplth 2, 2, 3
-; CHECK-NEXT:    stxvd2x 34, 0, 3
 ; CHECK-NEXT:    neg 4, 4
 ; CHECK-NEXT:    mtvsrd 35, 4
+; CHECK-NEXT:    vsplth 2, 2, 3
+; CHECK-NEXT:    stxvd2x 34, 0, 3
 ; CHECK-NEXT:    vsplth 3, 3, 3
 ; CHECK-NEXT:    stxvd2x 35, 0, 3
 bb: