Skip to content

Commit b7f5074

Browse files
arsenmarsenm
committed
CodeGen: Make target overrides of PointerLikeRegClass mandatory
Most targets should now use the convenience multiclass to fixup the operand definitions of pointer-using pseudoinstructions: defm : RemapAllTargetPseudoPointerOperands<target_ptr_regclass>;
1 parent 7bdd6d6 commit b7f5074

File tree

8 files changed

+64
-12
lines changed

8 files changed

+64
-12
lines changed

‎llvm/test/TableGen/DuplicateFieldValues.td‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -82,3 +82,4 @@ let BaseName = "0" in {
8282
def E0 : I, ABCRel, isEForm;
8383
}
8484

85+
defm : RemapAllTargetPseudoPointerOperands<DFVRegClass>;

‎llvm/test/TableGen/RegClassByHwMode.td‎

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ include "llvm/Target/Target.td"
1111
// INSTRINFO-NEXT: namespace llvm::MyTarget {
1212
// INSTRINFO-NEXT: enum {
1313
// INSTRINFO-NEXT: PHI
14+
// INSTRINFO: LOAD_STACK_GUARD = [[LOAD_STACK_GUARD_OPCODE:[0-9]+]]
1415
// INSTRINFO: };
1516
// INSTRINFO: enum RegClassByHwModeUses : uint16_t {
1617
// INSTRINFO-NEXT: MyPtrRC,
@@ -19,10 +20,20 @@ include "llvm/Target/Target.td"
1920
// INSTRINFO-NEXT: };
2021
// INSTRINFO-NEXT: }
2122

23+
24+
// INSTRINFO: { [[LOAD_STACK_GUARD_OPCODE]], 1, 1, 0, 0, 0, 0, [[LOAD_STACK_GUARD_OP_INDEX:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
25+
26+
// INSTRINFO: /* [[LOAD_STACK_GUARD_OP_INDEX]] */ { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },
27+
// INSTRINFO: { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
28+
// INSTRINFO: { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
29+
// INSTRINFO: { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
30+
// INSTRINFO: { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
31+
2232
// INSTRINFO: { MyTarget::XRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2333
// INSTRINFO: { MyTarget::XRegs_EvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
34+
2435
// INSTRINFO: { MyTarget::YRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },
25-
// INSTRINFO: { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },
36+
2637
// INSTRINFO: { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { MyTarget::MyPtrRC, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },
2738
// INSTRINFO: { MyTarget::YRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },
2839

@@ -463,5 +474,7 @@ def : Pat<
463474
(MY_LOAD $src)
464475
>;
465476

477+
defm : RemapAllTargetPseudoPointerOperands<XRegs_EvenIfRequired>;
478+
466479
def MyTargetISA : InstrInfo;
467480
def MyTarget : Target { let InstructionSet = MyTargetISA; }

‎llvm/test/TableGen/def-multiple-operands.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,3 +35,5 @@ def InstA : Instruction {
3535
field bits<8> SoftFail = 0;
3636
let hasSideEffects = false;
3737
}
38+
39+
defm : RemapAllTargetPseudoPointerOperands<P1>;

‎llvm/test/TableGen/get-named-operand-idx.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,8 @@ def InstD : InstBase {
4848
let UseNamedOperandTable = 0;
4949
}
5050

51+
defm : RemapAllTargetPseudoPointerOperands<RegClass>;
52+
5153
// CHECK-LABEL: #ifdef GET_INSTRINFO_OPERAND_ENUM
5254
// CHECK-NEXT: #undef GET_INSTRINFO_OPERAND_ENUM
5355
// CHECK-NEXT: namespace llvm::MyNamespace {

‎llvm/test/TableGen/get-operand-type-no-expand.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,3 +46,5 @@ def InstA : Instruction {
4646
// CHECK-NOEXPAND: /* InstA */
4747
// CHECK-NOEXPAND-NEXT: i512complex, i8complex, i32imm,
4848
// CHECK-NOEXPAND: #endif // GET_INSTRINFO_OPERAND_TYPE
49+
50+
defm : RemapAllTargetPseudoPointerOperands<RegClass>;

‎llvm/test/TableGen/get-operand-type.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,8 @@ def OpB : Operand<i32>;
1818

1919
def RegOp : RegisterOperand<RegClass>;
2020

21+
defm : RemapAllTargetPseudoPointerOperands<RegClass>;
22+
2123
def InstA : Instruction {
2224
let Size = 1;
2325
let OutOperandList = (outs OpA:$a);

‎llvm/test/TableGen/target-specialized-pseudos.td‎

Lines changed: 26 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,11 @@
1-
// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s -DONECASE -o - | FileCheck -check-prefixes=CHECK,ONECASE %s
21
// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s -DALLCASES -o - | FileCheck -check-prefixes=CHECK,ALLCASES %s
3-
// RUN: not llvm-tblgen -gen-instr-info -I %p/../../include %s -DERROR -o /dev/null 2>&1 | FileCheck -check-prefix=ERROR %s
2+
// RUN: not llvm-tblgen -gen-instr-info -I %p/../../include %s -DONECASE -o /dev/null 2>&1 | FileCheck -check-prefixes=ERROR-MISSING %s
3+
// RUN: not llvm-tblgen -gen-instr-info -I %p/../../include %s -DMULTIPLE_OVERRIDE_ERROR -o /dev/null 2>&1 | FileCheck -implicit-check-not=error: -check-prefix=MULTIPLE-OVERRIDE-ERROR %s
4+
// RUN: not llvm-tblgen -gen-instr-info -I %p/../../include %s -DALLCASES -DERROR_NONPSEUDO -o /dev/null 2>&1 | FileCheck -implicit-check-not=error: -check-prefix=ERROR-NONPSEUDO %s
5+
6+
7+
// def PREALLOCATED_ARG : StandardPseudoInstruction {
8+
49

510
// CHECK: namespace llvm::MyTarget {
611
// CHECK: enum {
@@ -20,17 +25,13 @@
2025
// CHECK-NEXT: { [[MY_MOV_OPCODE]], 2, 1, 2, 0, 0, 0, {{[0-9]+}}, MyTargetImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MY_MOV
2126
// CHECK-NEXT: { [[G_UBFX_OPCODE]], 4, 1, 0, 0, 0, 0, {{[0-9]+}}, MyTargetImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
2227

23-
// ONECASE: { [[LOAD_STACK_GUARD_OPCODE]], 1, 1, 0, 0, 0, 0, [[LOAD_STACK_GUARD_OP_ENTRY:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MY_LOAD_STACK_GUARD
24-
2528
// ALLCASES: { [[PATCHABLE_TYPED_EVENT_CALL_OPCODE]], 3, 0, 0, 0, 0, 0, [[PATCHABLE_TYPED_EVENT_CALL_OP_ENTRY:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
2629
// ALLCASES: { [[PATCHABLE_EVENT_CALL_OPCODE]], 2, 0, 0, 0, 0, 0, [[PATCHABLE_EVENT_CALL_OP_ENTRY:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
2730
// ALLCASES: { [[PREALLOCATED_ARG_OPCODE]], 3, 1, 0, 0, 0, 0, [[PREALLOCATED_ARG_OP_ENTRY:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
2831
// ALLCASES: { [[LOAD_STACK_GUARD_OPCODE]], 1, 1, 0, 0, 0, 0, [[LOAD_STACK_GUARD_OP_ENTRY:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
2932

3033
// CHECK: /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3134

32-
// ONECASE: /* [[LOAD_STACK_GUARD_OP_ENTRY]] */ { MyTarget::XRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
33-
3435
// ALLCASES: /* [[LOAD_STACK_GUARD_OP_ENTRY]] */ { MyTarget::XRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3536
// ALLCASES: /* [[PREALLOCATED_ARG_OP_ENTRY]] */ { MyTarget::XRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3637
// ALLCASES: /* [[PATCHABLE_EVENT_CALL_OP_ENTRY]] */ { MyTarget::XRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
@@ -72,6 +73,10 @@ def MY_LOAD_STACK_GUARD :
7273
let OutOperandList = (outs XRegs:$dst);
7374
}
7475

76+
// ERROR-MISSING: error: missing target override for pseudoinstruction using PointerLikeRegClass
77+
// ERROR-MISSING note: target should define equivalent instruction with RegisterClassLike replacement; (use RemapAllTargetPseudoPointerOperands?)
78+
79+
7580
#endif
7681

7782
#ifdef ALLCASES
@@ -81,15 +86,28 @@ defm my_remaps : RemapAllTargetPseudoPointerOperands<XRegs>;
8186
#endif
8287

8388

84-
#ifdef ERROR
89+
#ifdef MULTIPLE_OVERRIDE_ERROR
8590

8691
def MY_LOAD_STACK_GUARD_0 : TargetSpecializedStandardPseudoInstruction<LOAD_STACK_GUARD>;
8792

88-
// ERROR: :[[@LINE+1]]:5: error: multiple overrides of 'LOAD_STACK_GUARD' defined
93+
// MULTIPLE-OVERRIDE-ERROR: :[[@LINE+1]]:5: error: multiple overrides of 'LOAD_STACK_GUARD' defined
8994
def MY_LOAD_STACK_GUARD_1 : TargetSpecializedStandardPseudoInstruction<LOAD_STACK_GUARD>;
9095

9196
#endif
9297

98+
#ifdef ERROR_NONPSEUDO
99+
100+
// FIXME: Double error
101+
// ERROR-NONPSEUDO: [[@LINE+2]]:5: error: non-pseudoinstruction user of PointerLikeRegClass
102+
// ERROR-NONPSEUDO: [[@LINE+1]]:5: error: non-pseudoinstruction user of PointerLikeRegClass
103+
def NON_PSEUDO : TestInstruction {
104+
let OutOperandList = (outs XRegs:$dst);
105+
let InOperandList = (ins ptr_rc:$src);
106+
let AsmString = "non_pseudo $dst, $src";
107+
}
108+
109+
#endif
110+
93111
def MY_MOV : TestInstruction {
94112
let OutOperandList = (outs XRegs:$dst);
95113
let InOperandList = (ins XRegs:$src);

‎llvm/utils/TableGen/InstrInfoEmitter.cpp‎

Lines changed: 15 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -162,9 +162,21 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
162162
Res += ", ";
163163
} else if (OpR->isSubClassOf("RegisterClass"))
164164
Res += getQualifiedName(OpR) + "RegClassID, ";
165-
else if (OpR->isSubClassOf("PointerLikeRegClass"))
166-
Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
167-
else
165+
else if (OpR->isSubClassOf("PointerLikeRegClass")) {
166+
if (Inst.isPseudo) {
167+
// TODO: Verify this is a fixed pseudo
168+
PrintError(Inst.TheDef,
169+
"missing target override for pseudoinstruction "
170+
"using PointerLikeRegClass");
171+
PrintNote(OpR->getLoc(),
172+
"target should define equivalent instruction "
173+
"with RegisterClassLike replacement; (use "
174+
"RemapAllTargetPseudoPointerOperands?)");
175+
} else {
176+
PrintError(Inst.TheDef,
177+
"non-pseudoinstruction user of PointerLikeRegClass");
178+
}
179+
} else
168180
// -1 means the operand does not have a fixed register class.
169181
Res += "-1, ";
170182

0 commit comments

Comments
 (0)