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Polish the description of LowLevelInstMatcherDSL
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bolt/include/bolt/Core/MCInstUtils.h

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -184,17 +184,17 @@ static inline raw_ostream &operator<<(raw_ostream &OS,
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/// operands.
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///
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/// The goals of this DSL include
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/// * matching a single instruction against a template consisting of the
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/// * matching a single instruction against the template consisting of the
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/// particular target-specific opcode and a pattern of operands
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/// * matching operands against the known values (such as 42, AArch64::X1 or
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/// "the value of --brk-operand=N command line argument")
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/// * capturing operands of an instruction ("whatever is the destination
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/// register of AArch64::ADDXri instruction, store it to Xd variable to be
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/// queried later")
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/// * expressing repeated operands of a single matched instruction (such as
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/// "ADDXri Xd, Xd, 42, 0" for an arbitrary register Xm) as well as across
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/// multiple calls to matchInst(), which is naturally achieved by combining
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/// capturing operands and matching against the known values
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/// "ADDXri Xd, Xd, 42, 0" for an arbitrary register Xd) as well as across
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/// multiple calls to matchInst(), which is naturally achieved by sequentially
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/// capturing the operands and matching operands against the known values
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/// * matching multi-instruction code patterns by sequentially calling
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/// matchInst() while passing around already matched operands
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///
@@ -203,10 +203,10 @@ static inline raw_ostream &operator<<(raw_ostream &OS,
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/// * encapsulation of target-specific knowledge ("match an increment of Xm
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/// by 42")
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///
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/// Unlike MCPlusBuilder::MCInstMatcher, this matchInst() function focuses on
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/// the cases where a precise control over the instruction order is important.
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/// For example, one has to match two particular instructions against the
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/// following pattern (for two different registers Xm and Xn)
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/// Unlike MCPlusBuilder::MCInstMatcher, this DSL focuses on the use cases when
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/// the precise control over the instruction order is important. For example,
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/// let's consider a target-specific function that has to match two particular
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/// instructions against this pattern (for two different registers Xm and Xn)
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///
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/// ADDXrs Xm, Xn, Xm, #0
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/// BR Xm
@@ -225,7 +225,7 @@ static inline raw_ostream &operator<<(raw_ostream &OS,
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/// // Match the 0th operand against Xm:
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/// if (!matchInst(MaybeBr, AArch64::BR, Xm))
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/// return AArch64::NoRegister;
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/// // Manually check that Xm and Xn did not match the same register.
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/// // Manually check that Xm and Xn did not match the same register:
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/// if (Xm.get() == Xn.get())
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/// return AArch64::NoRegister;
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/// // Return the matched register:

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