@@ -184,17 +184,17 @@ static inline raw_ostream &operator<<(raw_ostream &OS,
184184// / operands.
185185// /
186186// / The goals of this DSL include
187- // / * matching a single instruction against a template consisting of the
187+ // / * matching a single instruction against the template consisting of the
188188// / particular target-specific opcode and a pattern of operands
189189// / * matching operands against the known values (such as 42, AArch64::X1 or
190190// / "the value of --brk-operand=N command line argument")
191191// / * capturing operands of an instruction ("whatever is the destination
192192// / register of AArch64::ADDXri instruction, store it to Xd variable to be
193193// / queried later")
194194// / * expressing repeated operands of a single matched instruction (such as
195- // / "ADDXri Xd, Xd, 42, 0" for an arbitrary register Xm ) as well as across
196- // / multiple calls to matchInst(), which is naturally achieved by combining
197- // / capturing operands and matching against the known values
195+ // / "ADDXri Xd, Xd, 42, 0" for an arbitrary register Xd ) as well as across
196+ // / multiple calls to matchInst(), which is naturally achieved by sequentially
197+ // / capturing the operands and matching operands against the known values
198198// / * matching multi-instruction code patterns by sequentially calling
199199// / matchInst() while passing around already matched operands
200200// /
@@ -203,10 +203,10 @@ static inline raw_ostream &operator<<(raw_ostream &OS,
203203// / * encapsulation of target-specific knowledge ("match an increment of Xm
204204// / by 42")
205205// /
206- // / Unlike MCPlusBuilder::MCInstMatcher, this matchInst() function focuses on
207- // / the cases where a precise control over the instruction order is important.
208- // / For example, one has to match two particular instructions against the
209- // / following pattern (for two different registers Xm and Xn)
206+ // / Unlike MCPlusBuilder::MCInstMatcher, this DSL focuses on the use cases when
207+ // / the precise control over the instruction order is important. For example,
208+ // / let's consider a target-specific function that has to match two particular
209+ // / instructions against this pattern (for two different registers Xm and Xn)
210210// /
211211// / ADDXrs Xm, Xn, Xm, #0
212212// / BR Xm
@@ -225,7 +225,7 @@ static inline raw_ostream &operator<<(raw_ostream &OS,
225225// / // Match the 0th operand against Xm:
226226// / if (!matchInst(MaybeBr, AArch64::BR, Xm))
227227// / return AArch64::NoRegister;
228- // / // Manually check that Xm and Xn did not match the same register.
228+ // / // Manually check that Xm and Xn did not match the same register:
229229// / if (Xm.get() == Xn.get())
230230// / return AArch64::NoRegister;
231231// / // Return the matched register:
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