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[LLVM][AArch64] Refactor lowering of fixed length integer setcc operations. (#132434)
The original code is essentially performing isel during legalisation with the AArch64 specific nodes offering no additional value compared to ISD::SETCC.
1 parent a17d496 commit b0b97e3

12 files changed

+185
-391
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 42 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -2057,6 +2057,15 @@ void AArch64TargetLowering::addTypeForNEON(MVT VT) {
20572057
setOperationAction(ISD::READ_REGISTER, MVT::i128, Custom);
20582058
setOperationAction(ISD::WRITE_REGISTER, MVT::i128, Custom);
20592059
}
2060+
2061+
if (VT.isInteger()) {
2062+
// Let common code emit inverted variants of compares we do support.
2063+
setCondCodeAction(ISD::SETNE, VT, Expand);
2064+
setCondCodeAction(ISD::SETLE, VT, Expand);
2065+
setCondCodeAction(ISD::SETLT, VT, Expand);
2066+
setCondCodeAction(ISD::SETULE, VT, Expand);
2067+
setCondCodeAction(ISD::SETULT, VT, Expand);
2068+
}
20602069
}
20612070

20622071
bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT,
@@ -2581,31 +2590,21 @@ unsigned AArch64TargetLowering::ComputeNumSignBitsForTargetNode(
25812590
unsigned VTBits = VT.getScalarSizeInBits();
25822591
unsigned Opcode = Op.getOpcode();
25832592
switch (Opcode) {
2584-
case AArch64ISD::CMEQ:
2585-
case AArch64ISD::CMGE:
2586-
case AArch64ISD::CMGT:
2587-
case AArch64ISD::CMHI:
2588-
case AArch64ISD::CMHS:
2589-
case AArch64ISD::FCMEQ:
2590-
case AArch64ISD::FCMGE:
2591-
case AArch64ISD::FCMGT:
2592-
case AArch64ISD::CMEQz:
2593-
case AArch64ISD::CMGEz:
2594-
case AArch64ISD::CMGTz:
2595-
case AArch64ISD::CMLEz:
2596-
case AArch64ISD::CMLTz:
2597-
case AArch64ISD::FCMEQz:
2598-
case AArch64ISD::FCMGEz:
2599-
case AArch64ISD::FCMGTz:
2600-
case AArch64ISD::FCMLEz:
2601-
case AArch64ISD::FCMLTz:
2602-
// Compares return either 0 or all-ones
2603-
return VTBits;
2604-
case AArch64ISD::VASHR: {
2605-
unsigned Tmp =
2606-
DAG.ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
2607-
return std::min<uint64_t>(Tmp + Op.getConstantOperandVal(1), VTBits);
2608-
}
2593+
case AArch64ISD::FCMEQ:
2594+
case AArch64ISD::FCMGE:
2595+
case AArch64ISD::FCMGT:
2596+
case AArch64ISD::FCMEQz:
2597+
case AArch64ISD::FCMGEz:
2598+
case AArch64ISD::FCMGTz:
2599+
case AArch64ISD::FCMLEz:
2600+
case AArch64ISD::FCMLTz:
2601+
// Compares return either 0 or all-ones
2602+
return VTBits;
2603+
case AArch64ISD::VASHR: {
2604+
unsigned Tmp =
2605+
DAG.ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
2606+
return std::min<uint64_t>(Tmp + Op.getConstantOperandVal(1), VTBits);
2607+
}
26092608
}
26102609

26112610
return 1;
@@ -2812,19 +2811,9 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
28122811
MAKE_CASE(AArch64ISD::VASHR)
28132812
MAKE_CASE(AArch64ISD::VSLI)
28142813
MAKE_CASE(AArch64ISD::VSRI)
2815-
MAKE_CASE(AArch64ISD::CMEQ)
2816-
MAKE_CASE(AArch64ISD::CMGE)
2817-
MAKE_CASE(AArch64ISD::CMGT)
2818-
MAKE_CASE(AArch64ISD::CMHI)
2819-
MAKE_CASE(AArch64ISD::CMHS)
28202814
MAKE_CASE(AArch64ISD::FCMEQ)
28212815
MAKE_CASE(AArch64ISD::FCMGE)
28222816
MAKE_CASE(AArch64ISD::FCMGT)
2823-
MAKE_CASE(AArch64ISD::CMEQz)
2824-
MAKE_CASE(AArch64ISD::CMGEz)
2825-
MAKE_CASE(AArch64ISD::CMGTz)
2826-
MAKE_CASE(AArch64ISD::CMLEz)
2827-
MAKE_CASE(AArch64ISD::CMLTz)
28282817
MAKE_CASE(AArch64ISD::FCMEQz)
28292818
MAKE_CASE(AArch64ISD::FCMGEz)
28302819
MAKE_CASE(AArch64ISD::FCMGTz)
@@ -15840,9 +15829,6 @@ static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
1584015829
SplatBitSize, HasAnyUndefs);
1584115830

1584215831
bool IsZero = IsCnst && SplatValue == 0;
15843-
bool IsOne =
15844-
IsCnst && SrcVT.getScalarSizeInBits() == SplatBitSize && SplatValue == 1;
15845-
bool IsMinusOne = IsCnst && SplatValue.isAllOnes();
1584615832

1584715833
if (SrcVT.getVectorElementType().isFloatingPoint()) {
1584815834
switch (CC) {
@@ -15889,50 +15875,7 @@ static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
1588915875
}
1589015876
}
1589115877

15892-
switch (CC) {
15893-
default:
15894-
return SDValue();
15895-
case AArch64CC::NE: {
15896-
SDValue Cmeq;
15897-
if (IsZero)
15898-
Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
15899-
else
15900-
Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
15901-
return DAG.getNOT(dl, Cmeq, VT);
15902-
}
15903-
case AArch64CC::EQ:
15904-
if (IsZero)
15905-
return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
15906-
return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
15907-
case AArch64CC::GE:
15908-
if (IsZero)
15909-
return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
15910-
return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
15911-
case AArch64CC::GT:
15912-
if (IsZero)
15913-
return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
15914-
if (IsMinusOne)
15915-
return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
15916-
return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
15917-
case AArch64CC::LE:
15918-
if (IsZero)
15919-
return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
15920-
return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
15921-
case AArch64CC::LS:
15922-
return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
15923-
case AArch64CC::LO:
15924-
return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
15925-
case AArch64CC::LT:
15926-
if (IsZero)
15927-
return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
15928-
if (IsOne)
15929-
return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
15930-
return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
15931-
case AArch64CC::HI:
15932-
return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
15933-
case AArch64CC::HS:
15934-
return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
15935-
}
15878+
return SDValue();
1593615879
}
1593715880

1593815881
SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
@@ -15950,13 +15893,8 @@ SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
1595015893
EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
1595115894
SDLoc dl(Op);
1595215895

15953-
if (LHS.getValueType().getVectorElementType().isInteger()) {
15954-
assert(LHS.getValueType() == RHS.getValueType());
15955-
AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
15956-
SDValue Cmp =
15957-
EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
15958-
return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
15959-
}
15896+
if (LHS.getValueType().getVectorElementType().isInteger())
15897+
return Op;
1596015898

1596115899
// Lower isnan(x) | isnan(never-nan) to x != x.
1596215900
// Lower !isnan(x) & !isnan(never-nan) to x == x.
@@ -18152,7 +18090,9 @@ static SDValue foldVectorXorShiftIntoCmp(SDNode *N, SelectionDAG &DAG,
1815218090
if (!ShiftAmt || ShiftAmt->getZExtValue() != ShiftEltTy.getSizeInBits() - 1)
1815318091
return SDValue();
1815418092

18155-
return DAG.getNode(AArch64ISD::CMGEz, SDLoc(N), VT, Shift.getOperand(0));
18093+
SDLoc DL(N);
18094+
SDValue Zero = DAG.getConstant(0, DL, Shift.getValueType());
18095+
return DAG.getSetCC(DL, VT, Shift.getOperand(0), Zero, ISD::SETGE);
1815618096
}
1815718097

1815818098
// Given a vecreduce_add node, detect the below pattern and convert it to the
@@ -18763,7 +18703,8 @@ static SDValue performMulVectorCmpZeroCombine(SDNode *N, SelectionDAG &DAG) {
1876318703

1876418704
SDLoc DL(N);
1876518705
SDValue In = DAG.getNode(AArch64ISD::NVCAST, DL, HalfVT, Srl.getOperand(0));
18766-
SDValue CM = DAG.getNode(AArch64ISD::CMLTz, DL, HalfVT, In);
18706+
SDValue Zero = DAG.getConstant(0, DL, In.getValueType());
18707+
SDValue CM = DAG.getSetCC(DL, HalfVT, Zero, In, ISD::SETGT);
1876718708
return DAG.getNode(AArch64ISD::NVCAST, DL, VT, CM);
1876818709
}
1876918710

@@ -25292,6 +25233,16 @@ static SDValue performSETCCCombine(SDNode *N,
2529225233
if (SDValue V = performOrXorChainCombine(N, DAG))
2529325234
return V;
2529425235

25236+
EVT CmpVT = LHS.getValueType();
25237+
25238+
// NOTE: This exists as a combine only because it proved too awkward to match
25239+
// splat(1) across all the NEON types during isel.
25240+
APInt SplatLHSVal;
25241+
if (CmpVT.isInteger() && Cond == ISD::SETGT &&
25242+
ISD::isConstantSplatVector(LHS.getNode(), SplatLHSVal) &&
25243+
SplatLHSVal.isOne())
25244+
return DAG.getSetCC(DL, VT, DAG.getConstant(0, DL, CmpVT), RHS, ISD::SETGE);
25245+
2529525246
return SDValue();
2529625247
}
2529725248

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h‎

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -241,21 +241,11 @@ enum NodeType : unsigned {
241241
VSRI,
242242

243243
// Vector comparisons
244-
CMEQ,
245-
CMGE,
246-
CMGT,
247-
CMHI,
248-
CMHS,
249244
FCMEQ,
250245
FCMGE,
251246
FCMGT,
252247

253248
// Vector zero comparisons
254-
CMEQz,
255-
CMGEz,
256-
CMGTz,
257-
CMLEz,
258-
CMLTz,
259249
FCMEQz,
260250
FCMGEz,
261251
FCMGTz,

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7086,7 +7086,7 @@ multiclass SIMD_FP8_CVTL<bits<2>sz, string asm, ValueType dty, SDPatternOperator
70867086
class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<2> size2,
70877087
bits<5> opcode, RegisterOperand regtype, string asm,
70887088
string kind, string zero, ValueType dty,
7089-
ValueType sty, SDNode OpNode>
7089+
ValueType sty, SDPatternOperator OpNode>
70907090
: I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
70917091
"{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
70927092
"|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
@@ -7110,7 +7110,7 @@ class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<2> size2,
71107110

71117111
// Comparisons support all element sizes, except 1xD.
71127112
multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
7113-
SDNode OpNode> {
7113+
SDPatternOperator OpNode> {
71147114
def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, 0b00, opc, V64,
71157115
asm, ".8b", "0",
71167116
v8i8, v8i8, OpNode>;
@@ -7981,7 +7981,7 @@ multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
79817981
SDPatternOperator OpNode> {
79827982
def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, 0b00, opc, FPR64, asm, "0">;
79837983

7984-
def : Pat<(v1i64 (OpNode FPR64:$Rn)),
7984+
def : Pat<(v1i64 (OpNode v1i64:$Rn)),
79857985
(!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
79867986
}
79877987

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 24 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -846,23 +846,35 @@ def AArch64vsri : SDNode<"AArch64ISD::VSRI", SDT_AArch64vshiftinsert>;
846846

847847
def AArch64bsp: SDNode<"AArch64ISD::BSP", SDT_AArch64trivec>;
848848

849-
def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
850-
def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
851-
def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
852-
def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
853-
def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
849+
def AArch64cmeq : PatFrag<(ops node:$lhs, node:$rhs),
850+
(setcc node:$lhs, node:$rhs, SETEQ)>;
851+
def AArch64cmge : PatFrag<(ops node:$lhs, node:$rhs),
852+
(setcc node:$lhs, node:$rhs, SETGE)>;
853+
def AArch64cmgt : PatFrag<(ops node:$lhs, node:$rhs),
854+
(setcc node:$lhs, node:$rhs, SETGT)>;
855+
def AArch64cmhi : PatFrag<(ops node:$lhs, node:$rhs),
856+
(setcc node:$lhs, node:$rhs, SETUGT)>;
857+
def AArch64cmhs : PatFrag<(ops node:$lhs, node:$rhs),
858+
(setcc node:$lhs, node:$rhs, SETUGE)>;
854859

855860
def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
856861
def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
857862
def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
858863

859-
def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
860-
def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
861-
def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
862-
def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
863-
def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
864+
def AArch64cmeqz : PatFrag<(ops node:$lhs),
865+
(setcc node:$lhs, immAllZerosV, SETEQ)>;
866+
def AArch64cmgez : PatFrags<(ops node:$lhs),
867+
[(setcc node:$lhs, immAllZerosV, SETGE),
868+
(setcc node:$lhs, immAllOnesV, SETGT)]>;
869+
def AArch64cmgtz : PatFrag<(ops node:$lhs),
870+
(setcc node:$lhs, immAllZerosV, SETGT)>;
871+
def AArch64cmlez : PatFrag<(ops node:$lhs),
872+
(setcc immAllZerosV, node:$lhs, SETGE)>;
873+
def AArch64cmltz : PatFrag<(ops node:$lhs),
874+
(setcc immAllZerosV, node:$lhs, SETGT)>;
875+
864876
def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
865-
(vnot (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
877+
(vnot (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
866878

867879
def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
868880
def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
@@ -5671,7 +5683,7 @@ defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
56715683
defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
56725684
defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
56735685
foreach VT = [ v8i8, v16i8, v4i16, v8i16, v2i32, v4i32, v2i64 ] in {
5674-
def : Pat<(vnot (AArch64cmeqz VT:$Rn)), (!cast<Instruction>("CMTST"#VT) VT:$Rn, VT:$Rn)>;
5686+
def : Pat<(VT (vnot (AArch64cmeqz VT:$Rn))), (!cast<Instruction>("CMTST"#VT) VT:$Rn, VT:$Rn)>;
56755687
}
56765688
defm FABD : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>;
56775689
let Predicates = [HasNEON] in {

‎llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll‎

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -352,17 +352,16 @@ define void @typei1_orig(i64 %a, ptr %p, ptr %q) {
352352
;
353353
; CHECK-GI-LABEL: typei1_orig:
354354
; CHECK-GI: // %bb.0:
355-
; CHECK-GI-NEXT: ldr q1, [x2]
355+
; CHECK-GI-NEXT: ldr q0, [x2]
356356
; CHECK-GI-NEXT: cmp x0, #0
357-
; CHECK-GI-NEXT: movi v0.2d, #0xffffffffffffffff
358357
; CHECK-GI-NEXT: cset w8, gt
359-
; CHECK-GI-NEXT: neg v1.8h, v1.8h
360-
; CHECK-GI-NEXT: dup v2.8h, w8
361-
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
362-
; CHECK-GI-NEXT: mul v1.8h, v1.8h, v2.8h
363-
; CHECK-GI-NEXT: cmeq v1.8h, v1.8h, #0
358+
; CHECK-GI-NEXT: neg v0.8h, v0.8h
359+
; CHECK-GI-NEXT: dup v1.8h, w8
360+
; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h
361+
; CHECK-GI-NEXT: movi v1.2d, #0xffffffffffffffff
362+
; CHECK-GI-NEXT: cmtst v0.8h, v0.8h, v0.8h
364363
; CHECK-GI-NEXT: mvn v1.16b, v1.16b
365-
; CHECK-GI-NEXT: uzp1 v0.16b, v1.16b, v0.16b
364+
; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b
366365
; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
367366
; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
368367
; CHECK-GI-NEXT: str q0, [x1]

‎llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2382,11 +2382,11 @@ define <2 x i1> @test_signed_v2f64_v2i1(<2 x double> %f) {
23822382
; CHECK-GI-LABEL: test_signed_v2f64_v2i1:
23832383
; CHECK-GI: // %bb.0:
23842384
; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d
2385-
; CHECK-GI-NEXT: movi v2.2d, #0xffffffffffffffff
23862385
; CHECK-GI-NEXT: cmlt v1.2d, v0.2d, #0
23872386
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2388-
; CHECK-GI-NEXT: cmgt v1.2d, v0.2d, v2.2d
2389-
; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b
2387+
; CHECK-GI-NEXT: movi v1.2d, #0xffffffffffffffff
2388+
; CHECK-GI-NEXT: cmge v2.2d, v0.2d, #0
2389+
; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
23902390
; CHECK-GI-NEXT: xtn v0.2s, v0.2d
23912391
; CHECK-GI-NEXT: ret
23922392
%x = call <2 x i1> @llvm.fptosi.sat.v2f64.v2i1(<2 x double> %f)

‎llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll‎

Lines changed: 5 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1499,8 +1499,7 @@ define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
14991499
;
15001500
; CHECK-GI-LABEL: vselect_cmpz_ne:
15011501
; CHECK-GI: // %bb.0:
1502-
; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, #0
1503-
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1502+
; CHECK-GI-NEXT: cmtst v0.8b, v0.8b, v0.8b
15041503
; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
15051504
; CHECK-GI-NEXT: ret
15061505
%cmp = icmp ne <8 x i8> %a, zeroinitializer
@@ -1533,17 +1532,10 @@ define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
15331532
}
15341533

15351534
define <8 x i8> @sext_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1536-
; CHECK-SD-LABEL: sext_tst:
1537-
; CHECK-SD: // %bb.0:
1538-
; CHECK-SD-NEXT: cmtst v0.8b, v0.8b, v1.8b
1539-
; CHECK-SD-NEXT: ret
1540-
;
1541-
; CHECK-GI-LABEL: sext_tst:
1542-
; CHECK-GI: // %bb.0:
1543-
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1544-
; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, #0
1545-
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1546-
; CHECK-GI-NEXT: ret
1535+
; CHECK-LABEL: sext_tst:
1536+
; CHECK: // %bb.0:
1537+
; CHECK-NEXT: cmtst v0.8b, v0.8b, v1.8b
1538+
; CHECK-NEXT: ret
15471539
%tmp3 = and <8 x i8> %a, %b
15481540
%tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
15491541
%d = sext <8 x i1> %tmp4 to <8 x i8>

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