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[TII][RISCV] Add renamable bit to copyPhysReg (#91179)
The renamable flag is useful during MachineCopyPropagation but renamable flag will be dropped after lowerCopy in some case. This patch introduces extra arguments to pass the renamable flag to copyPhysReg.
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59 files changed

+163
-61
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1018,10 +1018,16 @@ class TargetInstrInfo : public MCInstrInfo {
10181018
/// The source and destination registers may overlap, which may require a
10191019
/// careful implementation when multiple copy instructions are required for
10201020
/// large registers. See for example the ARM target.
1021+
///
1022+
/// If RenamableDest is true, the copy instruction's destination operand is
1023+
/// marked renamable.
1024+
/// If RenamableSrc is true, the copy instruction's source operand is
1025+
/// marked renamable.
10211026
virtual void copyPhysReg(MachineBasicBlock &MBB,
10221027
MachineBasicBlock::iterator MI, const DebugLoc &DL,
1023-
MCRegister DestReg, MCRegister SrcReg,
1024-
bool KillSrc) const {
1028+
MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
1029+
bool RenamableDest = false,
1030+
bool RenamableSrc = false) const {
10251031
llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
10261032
}
10271033

‎llvm/lib/CodeGen/TargetInstrInfo.cpp‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -823,7 +823,9 @@ void TargetInstrInfo::lowerCopy(MachineInstr *MI,
823823
}
824824

825825
copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), DstMO.getReg(),
826-
SrcMO.getReg(), SrcMO.isKill());
826+
SrcMO.getReg(), SrcMO.isKill(),
827+
DstMO.getReg().isPhysical() ? DstMO.isRenamable() : false,
828+
SrcMO.getReg().isPhysical() ? SrcMO.isRenamable() : false);
827829

828830
if (MI->getNumOperands() > 2)
829831
transferImplicitOperands(MI, TRI);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4851,7 +4851,9 @@ void AArch64InstrInfo::copyGPRRegTuple(MachineBasicBlock &MBB,
48514851
void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
48524852
MachineBasicBlock::iterator I,
48534853
const DebugLoc &DL, MCRegister DestReg,
4854-
MCRegister SrcReg, bool KillSrc) const {
4854+
MCRegister SrcReg, bool KillSrc,
4855+
bool RenamableDest,
4856+
bool RenamableSrc) const {
48554857
if (AArch64::GPR32spRegClass.contains(DestReg) &&
48564858
(AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
48574859
const TargetRegisterInfo *TRI = &getRegisterInfo();

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -344,7 +344,8 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
344344
llvm::ArrayRef<unsigned> Indices) const;
345345
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
346346
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
347-
bool KillSrc) const override;
347+
bool KillSrc, bool RenamableDest = false,
348+
bool RenamableSrc = false) const override;
348349

349350
void storeRegToStackSlot(MachineBasicBlock &MBB,
350351
MachineBasicBlock::iterator MBBI, Register SrcReg,

‎llvm/lib/Target/AMDGPU/R600InstrInfo.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,8 @@ bool R600InstrInfo::isVector(const MachineInstr &MI) const {
4040
void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4141
MachineBasicBlock::iterator MI,
4242
const DebugLoc &DL, MCRegister DestReg,
43-
MCRegister SrcReg, bool KillSrc) const {
43+
MCRegister SrcReg, bool KillSrc,
44+
bool RenamableDest, bool RenamableSrc) const {
4445
unsigned VectorComponents = 0;
4546
if ((R600::R600_Reg128RegClass.contains(DestReg) ||
4647
R600::R600_Reg128VerticalRegClass.contains(DestReg)) &&

‎llvm/lib/Target/AMDGPU/R600InstrInfo.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,8 @@ class R600InstrInfo final : public R600GenInstrInfo {
7373

7474
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
7575
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
76-
bool KillSrc) const override;
76+
bool KillSrc, bool RenamableDest = false,
77+
bool RenamableSrc = false) const override;
7778
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
7879
MachineBasicBlock::iterator MBBI) const override;
7980

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -794,7 +794,8 @@ static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,
794794
void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
795795
MachineBasicBlock::iterator MI,
796796
const DebugLoc &DL, MCRegister DestReg,
797-
MCRegister SrcReg, bool KillSrc) const {
797+
MCRegister SrcReg, bool KillSrc,
798+
bool RenamableDest, bool RenamableSrc) const {
798799
const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg);
799800
unsigned Size = RI.getRegSizeInBits(*RC);
800801
const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg);

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -255,7 +255,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
255255

256256
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
257257
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
258-
bool KillSrc) const override;
258+
bool KillSrc, bool RenamableDest = false,
259+
bool RenamableSrc = false) const override;
259260

260261
void materializeImmediate(MachineBasicBlock &MBB,
261262
MachineBasicBlock::iterator MI, const DebugLoc &DL,

‎llvm/lib/Target/ARC/ARCInstrInfo.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -281,7 +281,8 @@ unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
281281
void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
282282
MachineBasicBlock::iterator I,
283283
const DebugLoc &DL, MCRegister DestReg,
284-
MCRegister SrcReg, bool KillSrc) const {
284+
MCRegister SrcReg, bool KillSrc,
285+
bool RenamableDest, bool RenamableSrc) const {
285286
assert(ARC::GPR32RegClass.contains(SrcReg) &&
286287
"Only GPR32 src copy supported.");
287288
assert(ARC::GPR32RegClass.contains(DestReg) &&

‎llvm/lib/Target/ARC/ARCInstrInfo.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,8 @@ class ARCInstrInfo : public ARCGenInstrInfo {
6565

6666
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
6767
const DebugLoc &, MCRegister DestReg, MCRegister SrcReg,
68-
bool KillSrc) const override;
68+
bool KillSrc, bool RenamableDest = false,
69+
bool RenamableSrc = false) const override;
6970

7071
void storeRegToStackSlot(MachineBasicBlock &MBB,
7172
MachineBasicBlock::iterator MI, Register SrcReg,

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