Skip to content

Commit aef0e77

Browse files
RKSimonRKSimon
authored
[DAG] visitAND - Fold (and (srl X, C), 1) -> (srl X, BW-1) for signbit extraction (#114992)
If we're masking the LSB of a SRL node result and that is shifting down an extended sign bit, see if we can change the SRL to shift down the MSB directly. These patterns can occur during legalisation when we've sign extended to a wider type but the SRL is still shifting from the subreg. Alternative to #114967 Fixes the remaining regression in #112588
1 parent d7979c1 commit aef0e77

File tree

10 files changed

+105
-115
lines changed

10 files changed

+105
-115
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7392,6 +7392,16 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
73927392
return DAG.getNode(ISD::AND, DL, VT, X,
73937393
DAG.getNOT(DL, DAG.getNode(Opc, DL, VT, Y, Z), VT));
73947394

7395+
// Fold (and (srl X, C), 1) -> (srl X, BW-1) for signbit extraction
7396+
// If we are shifting down an extended sign bit, see if we can simplify
7397+
// this to shifting the MSB directly to expose further simplifications.
7398+
// This pattern often appears after sext_inreg legalization.
7399+
APInt Amt;
7400+
if (sd_match(N, m_And(m_Srl(m_Value(X), m_ConstInt(Amt)), m_One())) &&
7401+
Amt.ult(BitWidth - 1) && Amt.uge(BitWidth - DAG.ComputeNumSignBits(X)))
7402+
return DAG.getNode(ISD::SRL, DL, VT, X,
7403+
DAG.getShiftAmountConstant(BitWidth - 1, VT, DL));
7404+
73957405
// Masking the negated extension of a boolean is just the zero-extended
73967406
// boolean:
73977407
// and (sub 0, zext(bool X)), 1 --> zext(bool X)

‎llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,8 +25,8 @@ define i1 @test_srem_even(i4 %X) nounwind {
2525
; CHECK: // %bb.0:
2626
; CHECK-NEXT: sbfx w8, w0, #0, #4
2727
; CHECK-NEXT: add w8, w8, w8, lsl #1
28-
; CHECK-NEXT: ubfx w9, w8, #7, #1
29-
; CHECK-NEXT: add w8, w9, w8, lsr #4
28+
; CHECK-NEXT: lsr w9, w8, #4
29+
; CHECK-NEXT: add w8, w9, w8, lsr #31
3030
; CHECK-NEXT: mov w9, #6 // =0x6
3131
; CHECK-NEXT: msub w8, w8, w9, w0
3232
; CHECK-NEXT: and w8, w8, #0xf

‎llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll

Lines changed: 12 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -115,11 +115,10 @@ define i1 @test_srem_even(i4 %X) nounwind {
115115
; ARM5-LABEL: test_srem_even:
116116
; ARM5: @ %bb.0:
117117
; ARM5-NEXT: lsl r1, r0, #28
118-
; ARM5-NEXT: mov r2, #1
119118
; ARM5-NEXT: asr r1, r1, #28
120119
; ARM5-NEXT: add r1, r1, r1, lsl #1
121-
; ARM5-NEXT: and r2, r2, r1, lsr #7
122-
; ARM5-NEXT: add r1, r2, r1, lsr #4
120+
; ARM5-NEXT: lsr r2, r1, #4
121+
; ARM5-NEXT: add r1, r2, r1, lsr #31
123122
; ARM5-NEXT: add r1, r1, r1, lsl #1
124123
; ARM5-NEXT: sub r0, r0, r1, lsl #1
125124
; ARM5-NEXT: and r0, r0, #15
@@ -131,11 +130,10 @@ define i1 @test_srem_even(i4 %X) nounwind {
131130
; ARM6-LABEL: test_srem_even:
132131
; ARM6: @ %bb.0:
133132
; ARM6-NEXT: lsl r1, r0, #28
134-
; ARM6-NEXT: mov r2, #1
135133
; ARM6-NEXT: asr r1, r1, #28
136134
; ARM6-NEXT: add r1, r1, r1, lsl #1
137-
; ARM6-NEXT: and r2, r2, r1, lsr #7
138-
; ARM6-NEXT: add r1, r2, r1, lsr #4
135+
; ARM6-NEXT: lsr r2, r1, #4
136+
; ARM6-NEXT: add r1, r2, r1, lsr #31
139137
; ARM6-NEXT: add r1, r1, r1, lsl #1
140138
; ARM6-NEXT: sub r0, r0, r1, lsl #1
141139
; ARM6-NEXT: and r0, r0, #15
@@ -148,8 +146,8 @@ define i1 @test_srem_even(i4 %X) nounwind {
148146
; ARM7: @ %bb.0:
149147
; ARM7-NEXT: sbfx r1, r0, #0, #4
150148
; ARM7-NEXT: add r1, r1, r1, lsl #1
151-
; ARM7-NEXT: ubfx r2, r1, #7, #1
152-
; ARM7-NEXT: add r1, r2, r1, lsr #4
149+
; ARM7-NEXT: lsr r2, r1, #4
150+
; ARM7-NEXT: add r1, r2, r1, lsr #31
153151
; ARM7-NEXT: add r1, r1, r1, lsl #1
154152
; ARM7-NEXT: sub r0, r0, r1, lsl #1
155153
; ARM7-NEXT: and r0, r0, #15
@@ -162,8 +160,8 @@ define i1 @test_srem_even(i4 %X) nounwind {
162160
; ARM8: @ %bb.0:
163161
; ARM8-NEXT: sbfx r1, r0, #0, #4
164162
; ARM8-NEXT: add r1, r1, r1, lsl #1
165-
; ARM8-NEXT: ubfx r2, r1, #7, #1
166-
; ARM8-NEXT: add r1, r2, r1, lsr #4
163+
; ARM8-NEXT: lsr r2, r1, #4
164+
; ARM8-NEXT: add r1, r2, r1, lsr #31
167165
; ARM8-NEXT: add r1, r1, r1, lsl #1
168166
; ARM8-NEXT: sub r0, r0, r1, lsl #1
169167
; ARM8-NEXT: and r0, r0, #15
@@ -176,8 +174,8 @@ define i1 @test_srem_even(i4 %X) nounwind {
176174
; NEON7: @ %bb.0:
177175
; NEON7-NEXT: sbfx r1, r0, #0, #4
178176
; NEON7-NEXT: add r1, r1, r1, lsl #1
179-
; NEON7-NEXT: ubfx r2, r1, #7, #1
180-
; NEON7-NEXT: add r1, r2, r1, lsr #4
177+
; NEON7-NEXT: lsr r2, r1, #4
178+
; NEON7-NEXT: add r1, r2, r1, lsr #31
181179
; NEON7-NEXT: add r1, r1, r1, lsl #1
182180
; NEON7-NEXT: sub r0, r0, r1, lsl #1
183181
; NEON7-NEXT: and r0, r0, #15
@@ -190,8 +188,8 @@ define i1 @test_srem_even(i4 %X) nounwind {
190188
; NEON8: @ %bb.0:
191189
; NEON8-NEXT: sbfx r1, r0, #0, #4
192190
; NEON8-NEXT: add r1, r1, r1, lsl #1
193-
; NEON8-NEXT: ubfx r2, r1, #7, #1
194-
; NEON8-NEXT: add r1, r2, r1, lsr #4
191+
; NEON8-NEXT: lsr r2, r1, #4
192+
; NEON8-NEXT: add r1, r2, r1, lsr #31
195193
; NEON8-NEXT: add r1, r1, r1, lsl #1
196194
; NEON8-NEXT: sub r0, r0, r1, lsl #1
197195
; NEON8-NEXT: and r0, r0, #15

‎llvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -47,17 +47,16 @@ define i1 @test_srem_even(i4 %X) nounwind {
4747
; MIPSEL-NEXT: sra $1, $1, 28
4848
; MIPSEL-NEXT: sll $2, $1, 1
4949
; MIPSEL-NEXT: addu $1, $2, $1
50-
; MIPSEL-NEXT: srl $2, $1, 4
51-
; MIPSEL-NEXT: srl $1, $1, 7
52-
; MIPSEL-NEXT: andi $1, $1, 1
53-
; MIPSEL-NEXT: addiu $3, $zero, 1
54-
; MIPSEL-NEXT: addu $1, $2, $1
55-
; MIPSEL-NEXT: sll $2, $1, 1
56-
; MIPSEL-NEXT: sll $1, $1, 2
50+
; MIPSEL-NEXT: srl $2, $1, 31
51+
; MIPSEL-NEXT: srl $1, $1, 4
5752
; MIPSEL-NEXT: addu $1, $1, $2
53+
; MIPSEL-NEXT: addiu $2, $zero, 1
54+
; MIPSEL-NEXT: sll $3, $1, 1
55+
; MIPSEL-NEXT: sll $1, $1, 2
56+
; MIPSEL-NEXT: addu $1, $1, $3
5857
; MIPSEL-NEXT: subu $1, $4, $1
5958
; MIPSEL-NEXT: andi $1, $1, 15
60-
; MIPSEL-NEXT: xor $1, $1, $3
59+
; MIPSEL-NEXT: xor $1, $1, $2
6160
; MIPSEL-NEXT: jr $ra
6261
; MIPSEL-NEXT: sltiu $2, $1, 1
6362
;
@@ -69,10 +68,9 @@ define i1 @test_srem_even(i4 %X) nounwind {
6968
; MIPS64EL-NEXT: sll $3, $2, 1
7069
; MIPS64EL-NEXT: addu $2, $3, $2
7170
; MIPS64EL-NEXT: addiu $3, $zero, 1
72-
; MIPS64EL-NEXT: srl $4, $2, 4
73-
; MIPS64EL-NEXT: srl $2, $2, 7
74-
; MIPS64EL-NEXT: andi $2, $2, 1
75-
; MIPS64EL-NEXT: addu $2, $4, $2
71+
; MIPS64EL-NEXT: srl $4, $2, 31
72+
; MIPS64EL-NEXT: srl $2, $2, 4
73+
; MIPS64EL-NEXT: addu $2, $2, $4
7674
; MIPS64EL-NEXT: sll $4, $2, 1
7775
; MIPS64EL-NEXT: sll $2, $2, 2
7876
; MIPS64EL-NEXT: addu $2, $2, $4

‎llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ define i1 @test_srem_even(i4 %X) nounwind {
4646
; PPC-NEXT: slwi 4, 3, 28
4747
; PPC-NEXT: srawi 4, 4, 28
4848
; PPC-NEXT: mulli 4, 4, 3
49-
; PPC-NEXT: rlwinm 5, 4, 25, 31, 31
49+
; PPC-NEXT: srwi 5, 4, 31
5050
; PPC-NEXT: srwi 4, 4, 4
5151
; PPC-NEXT: add 4, 4, 5
5252
; PPC-NEXT: mulli 4, 4, 6
@@ -65,7 +65,7 @@ define i1 @test_srem_even(i4 %X) nounwind {
6565
; PPC64LE-NEXT: srawi 4, 4, 28
6666
; PPC64LE-NEXT: slwi 5, 4, 1
6767
; PPC64LE-NEXT: add 4, 4, 5
68-
; PPC64LE-NEXT: rlwinm 5, 4, 25, 31, 31
68+
; PPC64LE-NEXT: srwi 5, 4, 31
6969
; PPC64LE-NEXT: srwi 4, 4, 4
7070
; PPC64LE-NEXT: add 4, 4, 5
7171
; PPC64LE-NEXT: mulli 4, 4, 6

‎llvm/test/CodeGen/RISCV/div-by-constant.ll

Lines changed: 28 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -488,21 +488,19 @@ define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {
488488
; RV32IM-NEXT: srai a0, a0, 24
489489
; RV32IM-NEXT: li a1, 86
490490
; RV32IM-NEXT: mul a0, a0, a1
491-
; RV32IM-NEXT: srli a1, a0, 8
492-
; RV32IM-NEXT: slli a0, a0, 16
493-
; RV32IM-NEXT: srli a0, a0, 31
494-
; RV32IM-NEXT: add a0, a1, a0
491+
; RV32IM-NEXT: srli a1, a0, 31
492+
; RV32IM-NEXT: srli a0, a0, 8
493+
; RV32IM-NEXT: add a0, a0, a1
495494
; RV32IM-NEXT: ret
496495
;
497496
; RV32IMZB-LABEL: sdiv8_constant_no_srai:
498497
; RV32IMZB: # %bb.0:
499498
; RV32IMZB-NEXT: sext.b a0, a0
500499
; RV32IMZB-NEXT: li a1, 86
501500
; RV32IMZB-NEXT: mul a0, a0, a1
502-
; RV32IMZB-NEXT: srli a1, a0, 8
503-
; RV32IMZB-NEXT: slli a0, a0, 16
504-
; RV32IMZB-NEXT: srli a0, a0, 31
505-
; RV32IMZB-NEXT: add a0, a1, a0
501+
; RV32IMZB-NEXT: srli a1, a0, 31
502+
; RV32IMZB-NEXT: srli a0, a0, 8
503+
; RV32IMZB-NEXT: add a0, a0, a1
506504
; RV32IMZB-NEXT: ret
507505
;
508506
; RV64IM-LABEL: sdiv8_constant_no_srai:
@@ -511,21 +509,19 @@ define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {
511509
; RV64IM-NEXT: srai a0, a0, 56
512510
; RV64IM-NEXT: li a1, 86
513511
; RV64IM-NEXT: mul a0, a0, a1
514-
; RV64IM-NEXT: srli a1, a0, 8
515-
; RV64IM-NEXT: slli a0, a0, 48
516-
; RV64IM-NEXT: srli a0, a0, 63
517-
; RV64IM-NEXT: add a0, a1, a0
512+
; RV64IM-NEXT: srli a1, a0, 63
513+
; RV64IM-NEXT: srli a0, a0, 8
514+
; RV64IM-NEXT: add a0, a0, a1
518515
; RV64IM-NEXT: ret
519516
;
520517
; RV64IMZB-LABEL: sdiv8_constant_no_srai:
521518
; RV64IMZB: # %bb.0:
522519
; RV64IMZB-NEXT: sext.b a0, a0
523520
; RV64IMZB-NEXT: li a1, 86
524521
; RV64IMZB-NEXT: mul a0, a0, a1
525-
; RV64IMZB-NEXT: srli a1, a0, 8
526-
; RV64IMZB-NEXT: slli a0, a0, 48
527-
; RV64IMZB-NEXT: srli a0, a0, 63
528-
; RV64IMZB-NEXT: add a0, a1, a0
522+
; RV64IMZB-NEXT: srli a1, a0, 63
523+
; RV64IMZB-NEXT: srli a0, a0, 8
524+
; RV64IMZB-NEXT: add a0, a0, a1
529525
; RV64IMZB-NEXT: ret
530526
%1 = sdiv i8 %a, 3
531527
ret i8 %1
@@ -538,21 +534,19 @@ define i8 @sdiv8_constant_srai(i8 %a) nounwind {
538534
; RV32IM-NEXT: srai a0, a0, 24
539535
; RV32IM-NEXT: li a1, 103
540536
; RV32IM-NEXT: mul a0, a0, a1
541-
; RV32IM-NEXT: srai a1, a0, 9
542-
; RV32IM-NEXT: slli a0, a0, 16
543-
; RV32IM-NEXT: srli a0, a0, 31
544-
; RV32IM-NEXT: add a0, a1, a0
537+
; RV32IM-NEXT: srli a1, a0, 31
538+
; RV32IM-NEXT: srai a0, a0, 9
539+
; RV32IM-NEXT: add a0, a0, a1
545540
; RV32IM-NEXT: ret
546541
;
547542
; RV32IMZB-LABEL: sdiv8_constant_srai:
548543
; RV32IMZB: # %bb.0:
549544
; RV32IMZB-NEXT: sext.b a0, a0
550545
; RV32IMZB-NEXT: li a1, 103
551546
; RV32IMZB-NEXT: mul a0, a0, a1
552-
; RV32IMZB-NEXT: srai a1, a0, 9
553-
; RV32IMZB-NEXT: slli a0, a0, 16
554-
; RV32IMZB-NEXT: srli a0, a0, 31
555-
; RV32IMZB-NEXT: add a0, a1, a0
547+
; RV32IMZB-NEXT: srli a1, a0, 31
548+
; RV32IMZB-NEXT: srai a0, a0, 9
549+
; RV32IMZB-NEXT: add a0, a0, a1
556550
; RV32IMZB-NEXT: ret
557551
;
558552
; RV64IM-LABEL: sdiv8_constant_srai:
@@ -561,21 +555,19 @@ define i8 @sdiv8_constant_srai(i8 %a) nounwind {
561555
; RV64IM-NEXT: srai a0, a0, 56
562556
; RV64IM-NEXT: li a1, 103
563557
; RV64IM-NEXT: mul a0, a0, a1
564-
; RV64IM-NEXT: srai a1, a0, 9
565-
; RV64IM-NEXT: slli a0, a0, 48
566-
; RV64IM-NEXT: srli a0, a0, 63
567-
; RV64IM-NEXT: add a0, a1, a0
558+
; RV64IM-NEXT: srli a1, a0, 63
559+
; RV64IM-NEXT: srai a0, a0, 9
560+
; RV64IM-NEXT: add a0, a0, a1
568561
; RV64IM-NEXT: ret
569562
;
570563
; RV64IMZB-LABEL: sdiv8_constant_srai:
571564
; RV64IMZB: # %bb.0:
572565
; RV64IMZB-NEXT: sext.b a0, a0
573566
; RV64IMZB-NEXT: li a1, 103
574567
; RV64IMZB-NEXT: mul a0, a0, a1
575-
; RV64IMZB-NEXT: srai a1, a0, 9
576-
; RV64IMZB-NEXT: slli a0, a0, 48
577-
; RV64IMZB-NEXT: srli a0, a0, 63
578-
; RV64IMZB-NEXT: add a0, a1, a0
568+
; RV64IMZB-NEXT: srli a1, a0, 63
569+
; RV64IMZB-NEXT: srai a0, a0, 9
570+
; RV64IMZB-NEXT: add a0, a0, a1
579571
; RV64IMZB-NEXT: ret
580572
%1 = sdiv i8 %a, 5
581573
ret i8 %1
@@ -728,7 +720,7 @@ define i16 @sdiv16_constant_no_srai(i16 %a) nounwind {
728720
; RV64IM-NEXT: lui a1, 5
729721
; RV64IM-NEXT: addiw a1, a1, 1366
730722
; RV64IM-NEXT: mul a0, a0, a1
731-
; RV64IM-NEXT: srliw a1, a0, 31
723+
; RV64IM-NEXT: srli a1, a0, 63
732724
; RV64IM-NEXT: srli a0, a0, 16
733725
; RV64IM-NEXT: add a0, a0, a1
734726
; RV64IM-NEXT: ret
@@ -739,7 +731,7 @@ define i16 @sdiv16_constant_no_srai(i16 %a) nounwind {
739731
; RV64IMZB-NEXT: lui a1, 5
740732
; RV64IMZB-NEXT: addiw a1, a1, 1366
741733
; RV64IMZB-NEXT: mul a0, a0, a1
742-
; RV64IMZB-NEXT: srliw a1, a0, 31
734+
; RV64IMZB-NEXT: srli a1, a0, 63
743735
; RV64IMZB-NEXT: srli a0, a0, 16
744736
; RV64IMZB-NEXT: add a0, a0, a1
745737
; RV64IMZB-NEXT: ret
@@ -778,7 +770,7 @@ define i16 @sdiv16_constant_srai(i16 %a) nounwind {
778770
; RV64IM-NEXT: lui a1, 6
779771
; RV64IM-NEXT: addiw a1, a1, 1639
780772
; RV64IM-NEXT: mul a0, a0, a1
781-
; RV64IM-NEXT: srliw a1, a0, 31
773+
; RV64IM-NEXT: srli a1, a0, 63
782774
; RV64IM-NEXT: srai a0, a0, 17
783775
; RV64IM-NEXT: add a0, a0, a1
784776
; RV64IM-NEXT: ret
@@ -789,7 +781,7 @@ define i16 @sdiv16_constant_srai(i16 %a) nounwind {
789781
; RV64IMZB-NEXT: lui a1, 6
790782
; RV64IMZB-NEXT: addiw a1, a1, 1639
791783
; RV64IMZB-NEXT: mul a0, a0, a1
792-
; RV64IMZB-NEXT: srliw a1, a0, 31
784+
; RV64IMZB-NEXT: srli a1, a0, 63
793785
; RV64IMZB-NEXT: srai a0, a0, 17
794786
; RV64IMZB-NEXT: add a0, a0, a1
795787
; RV64IMZB-NEXT: ret

‎llvm/test/CodeGen/RISCV/div.ll

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -980,10 +980,9 @@ define i8 @sdiv8_constant(i8 %a) nounwind {
980980
; RV32IM-NEXT: srai a0, a0, 24
981981
; RV32IM-NEXT: li a1, 103
982982
; RV32IM-NEXT: mul a0, a0, a1
983-
; RV32IM-NEXT: srai a1, a0, 9
984-
; RV32IM-NEXT: slli a0, a0, 16
985-
; RV32IM-NEXT: srli a0, a0, 31
986-
; RV32IM-NEXT: add a0, a1, a0
983+
; RV32IM-NEXT: srli a1, a0, 31
984+
; RV32IM-NEXT: srai a0, a0, 9
985+
; RV32IM-NEXT: add a0, a0, a1
987986
; RV32IM-NEXT: ret
988987
;
989988
; RV64I-LABEL: sdiv8_constant:
@@ -1004,10 +1003,9 @@ define i8 @sdiv8_constant(i8 %a) nounwind {
10041003
; RV64IM-NEXT: srai a0, a0, 56
10051004
; RV64IM-NEXT: li a1, 103
10061005
; RV64IM-NEXT: mul a0, a0, a1
1007-
; RV64IM-NEXT: srai a1, a0, 9
1008-
; RV64IM-NEXT: slli a0, a0, 48
1009-
; RV64IM-NEXT: srli a0, a0, 63
1010-
; RV64IM-NEXT: add a0, a1, a0
1006+
; RV64IM-NEXT: srli a1, a0, 63
1007+
; RV64IM-NEXT: srai a0, a0, 9
1008+
; RV64IM-NEXT: add a0, a0, a1
10111009
; RV64IM-NEXT: ret
10121010
%1 = sdiv i8 %a, 5
10131011
ret i8 %1
@@ -1193,7 +1191,7 @@ define i16 @sdiv16_constant(i16 %a) nounwind {
11931191
; RV64IM-NEXT: lui a1, 6
11941192
; RV64IM-NEXT: addiw a1, a1, 1639
11951193
; RV64IM-NEXT: mul a0, a0, a1
1196-
; RV64IM-NEXT: srliw a1, a0, 31
1194+
; RV64IM-NEXT: srli a1, a0, 63
11971195
; RV64IM-NEXT: srai a0, a0, 17
11981196
; RV64IM-NEXT: add a0, a0, a1
11991197
; RV64IM-NEXT: ret

0 commit comments

Comments
 (0)