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[RISCV] Add B extension
It seems that we have `B` extension again: https://github.com/riscv/riscv-b According to the spec, `B` extension represents the collection of the `Zba`, `Zbb`, `Zbs` extensions.
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‎clang/test/Driver/riscv-arch.c

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@@ -231,11 +231,6 @@
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// RV32-STD: error: invalid arch name 'rv32imqc',
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// RV32-STD: unsupported standard user-level extension 'q'
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// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
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// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
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// RV32-B: error: invalid arch name 'rv32ib',
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// RV32-B: unsupported standard user-level extension 'b'
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// RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
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// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
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// RV32X: error: invalid arch name 'rv32xabc',

‎clang/test/Preprocessor/riscv-target-features.c

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@@ -7,6 +7,7 @@
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// CHECK-NOT: __riscv_64e {{.*$}}
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// CHECK-NOT: __riscv_a {{.*$}}
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// CHECK-NOT: __riscv_atomic
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// CHECK-NOT: __riscv_b {{.*$}}
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// CHECK-NOT: __riscv_c {{.*$}}
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// CHECK-NOT: __riscv_compressed {{.*$}}
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// CHECK-NOT: __riscv_d {{.*$}}
@@ -194,6 +195,25 @@
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// CHECK-A-EXT: __riscv_a 2001000{{$}}
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// CHECK-A-EXT: __riscv_atomic 1
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ib -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64ib -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
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// CHECK-B-EXT: __riscv_b 1000000{{$}}
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// CHECK-B-EXT: __riscv_zba 1000000{{$}}
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// CHECK-B-EXT: __riscv_zbb 1000000{{$}}
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// CHECK-B-EXT: __riscv_zbs 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32i_zba_zbb_zbs -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-B %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64i_zba_zbb_zbs -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-B %s
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// CHECK-COMBINE-INTO-B: __riscv_b 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ic -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s

‎llvm/docs/RISCVUsage.rst

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@@ -85,6 +85,7 @@ on support follow.
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Extension Status
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================ =================================================================
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``A`` Supported
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``B`` Supported
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``C`` Supported
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``D`` Supported
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``F`` Supported

‎llvm/docs/ReleaseNotes.rst

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@@ -142,6 +142,7 @@ Changes to the RISC-V Backend
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* Zaamo and Zalrsc are no longer experimental.
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* Processors that enable post reg-alloc scheduling (PostMachineScheduler) by default should use the `UsePostRAScheduler` subtarget feature. Setting `PostRAScheduler = 1` in the scheduler model will have no effect on the enabling of the PostMachineScheduler.
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* Zabha is no longer experimental.
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* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -477,6 +477,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
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// Bitmanip Extensions for Cryptography Extensions
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def FeatureStdExtB
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: RISCVExtension<"b", 1, 0,
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"'B' (the collection of the Zba, Zbb, Zbs extensions)",
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[FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>;
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def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
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AssemblerPredicate<(all_of FeatureStdExtB),
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"'B' (the collection of the Zba, Zbb, Zbs extensions)">;
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def FeatureStdExtZbkb
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: RISCVExtension<"zbkb", 1, 0,
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"'Zbkb' (Bitmanip instructions for Cryptography)">;

‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -5,6 +5,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV32ZMMUL %s
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; RUN: llc -mtriple=riscv32 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV32MZMMUL %s
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; RUN: llc -mtriple=riscv32 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV32A %s
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; RUN: llc -mtriple=riscv32 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV32B %s
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; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV32F %s
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; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV32D %s
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; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV32C %s
@@ -131,6 +132,7 @@
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; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s
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; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s
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; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A %s
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; RUN: llc -mtriple=riscv64 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV64B %s
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; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s
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; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s
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; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV64C %s
@@ -277,6 +279,7 @@
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; RV32ZMMUL: .attribute 5, "rv32i2p1_zmmul1p0"
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; RV32MZMMUL: .attribute 5, "rv32i2p1_m2p0_zmmul1p0"
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; RV32A: .attribute 5, "rv32i2p1_a2p1"
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; RV32B: .attribute 5, "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
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; RV32F: .attribute 5, "rv32i2p1_f2p2_zicsr2p0"
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; RV32D: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0"
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; RV32C: .attribute 5, "rv32i2p1_c2p0"
@@ -402,6 +405,7 @@
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; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
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; RV64MZMMUL: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
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; RV64A: .attribute 5, "rv64i2p1_a2p1"
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; RV64B: .attribute 5, "rv64i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
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; RV64F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0"
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; RV64D: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0"
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; RV64C: .attribute 5, "rv64i2p1_c2p0"

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

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@@ -312,8 +312,6 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) {
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}
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TEST(ParseArchString, RejectsUnrecognizedExtensionNamesByDefault) {
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EXPECT_EQ(toString(RISCVISAInfo::parseArchString("rv64ib", true).takeError()),
316-
"unsupported standard user-level extension 'b'");
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EXPECT_EQ(
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toString(
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RISCVISAInfo::parseArchString("rv32i_zmadeup", true).takeError()),
@@ -326,9 +324,6 @@ TEST(ParseArchString, RejectsUnrecognizedExtensionNamesByDefault) {
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toString(
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RISCVISAInfo::parseArchString("rv64g_xmadeup", true).takeError()),
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"unsupported non-standard user-level extension 'xmadeup'");
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EXPECT_EQ(
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toString(RISCVISAInfo::parseArchString("rv64ib1p0", true).takeError()),
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"unsupported standard user-level extension 'b'");
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EXPECT_EQ(
333328
toString(
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RISCVISAInfo::parseArchString("rv32i_zmadeup1p0", true).takeError()),
@@ -344,8 +339,7 @@ TEST(ParseArchString, RejectsUnrecognizedExtensionNamesByDefault) {
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}
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TEST(ParseArchString, IgnoresUnrecognizedExtensionNamesWithIgnoreUnknown) {
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for (StringRef Input : {"rv32ib", "rv32i_zmadeup",
348-
"rv64i_smadeup", "rv64i_xmadeup"}) {
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for (StringRef Input : {"rv32i_zmadeup", "rv64i_smadeup", "rv64i_xmadeup"}) {
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auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true, false, true);
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ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
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RISCVISAInfo &Info = **MaybeISAInfo;
@@ -913,6 +907,7 @@ R"(All available -march extensions for RISC-V
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f 2.2
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d 2.2
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c 2.0
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b 1.0
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v 1.0
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h 1.0
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zic64b 1.0

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