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[Fix] code review.
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4 files changed

+9
-25
lines changed

4 files changed

+9
-25
lines changed

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -283,17 +283,6 @@ static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo,
283283
return MCDisassembler::Success;
284284
}
285285

286-
static DecodeStatus DecodeVREvenRegisterClass(MCInst &Inst, uint32_t RegNo,
287-
uint64_t Address,
288-
const MCDisassembler *Decoder) {
289-
if (RegNo >= 32 || RegNo % 2)
290-
return MCDisassembler::Fail;
291-
292-
MCRegister Reg = RISCV::V0 + RegNo;
293-
Inst.addOperand(MCOperand::createReg(Reg));
294-
return MCDisassembler::Success;
295-
}
296-
297286
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
298287
uint64_t Address,
299288
const MCDisassembler *Decoder) {

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,7 @@
66
//
77
//===----------------------------------------------------------------------===//
88
//
9-
// This file describes the xsmtvdot vendor extensions defined by SpacemiT.
10-
// NOTE: This extension instructions only support cases where LMUL is less than
11-
// or equal to 1
9+
// This file describes the vendor extensions defined by SpacemiT.
1210
//
1311
//===----------------------------------------------------------------------===//
1412

@@ -63,7 +61,7 @@ def SMT_VDot_Slide3 : SMTVEncoding2<0b10>;
6361
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
6462
// Base vector dot product (no slide) format.
6563
class RVInstSMTVDot<SMTVEncoding2 sign, string opcodestr, string argstr>
66-
: RVInst<(outs VREven:$vd), (ins VR:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> {
64+
: RVInst<(outs VRM2:$vd), (ins VR:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> {
6765
bits<5> vd;
6866
bits<5> vs1;
6967
bits<5> vs2;
@@ -80,7 +78,7 @@ class RVInstSMTVDot<SMTVEncoding2 sign, string opcodestr, string argstr>
8078

8179
// Sliding-window vector dot product format.
8280
class RVInstSMTVDotSlide<SMTVEncoding2 funct2, SMTVEncoding2 sign, string opcodestr, string argstr>
83-
: RVInst<(outs VREven:$vd), (ins VREven:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> {
81+
: RVInst<(outs VRM2:$vd), (ins VRM2:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> {
8482
bits<5> vd;
8583
bits<5> vs1;
8684
bits<5> vs2;

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.td‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -787,9 +787,6 @@ def VR : VReg<!listconcat(VM1VTs, VMaskVTs),
787787

788788
def VRNoV0 : VReg<!listconcat(VM1VTs, VMaskVTs), (sub VR, V0), 1>;
789789

790-
let GeneratePressureSet = false in
791-
def VREven : VReg<VM1VTs, (add (sequence "V%u", 0, 30, 2)), 1>;
792-
793790
def VRM2 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2),
794791
(sequence "V%uM2", 6, 0, 2)), 2>;
795792

‎llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ body: |
5555
; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF
5656
; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm2nov0 = INIT_UNDEF
5757
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_1
58-
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vreven = INIT_UNDEF
58+
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vr = INIT_UNDEF
5959
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm1_0
6060
; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
6161
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
@@ -131,7 +131,7 @@ body: |
131131
; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF
132132
; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm2 = INIT_UNDEF
133133
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_0
134-
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vreven_and_vrnov0 = INIT_UNDEF
134+
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrnov0 = INIT_UNDEF
135135
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm1_2
136136
; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
137137
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
@@ -284,7 +284,7 @@ body: |
284284
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1
285285
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF
286286
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_1
287-
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vreven = INIT_UNDEF
287+
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vr = INIT_UNDEF
288288
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_0
289289
; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
290290
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
@@ -364,7 +364,7 @@ body: |
364364
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1
365365
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2 = INIT_UNDEF
366366
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_0
367-
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vreven_and_vrnov0 = INIT_UNDEF
367+
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vrnov0 = INIT_UNDEF
368368
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_2
369369
; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
370370
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
@@ -444,7 +444,7 @@ body: |
444444
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0
445445
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF
446446
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_3
447-
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vreven_and_vrnov0 = INIT_UNDEF
447+
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vrnov0 = INIT_UNDEF
448448
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_4
449449
; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
450450
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
@@ -524,7 +524,7 @@ body: |
524524
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0
525525
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF
526526
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_2
527-
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vreven_and_vrnov0 = INIT_UNDEF
527+
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vrnov0 = INIT_UNDEF
528528
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_6
529529
; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
530530
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0

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