Skip to content

Commit a4286fc

Browse files
topperctopperc
committed
[X86] Fix usage of Align constructing MachineMemOperands.
Similar to D77687, but for the X86 specific code. Differential Revision: https://reviews.llvm.org/D79381
1 parent 52cc8ba commit a4286fc

File tree

2 files changed

+54
-49
lines changed

2 files changed

+54
-49
lines changed

‎llvm/lib/Target/X86/X86ISelLowering.cpp‎

Lines changed: 50 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -8340,7 +8340,8 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
83408340
"Cannot merge volatile or atomic loads.");
83418341
SDValue NewLd =
83428342
DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
8343-
LDBase->getPointerInfo(), LDBase->getAlignment(), MMOFlags);
8343+
LDBase->getPointerInfo(), LDBase->getOriginalAlign(),
8344+
MMOFlags);
83448345
for (auto *LD : Loads)
83458346
if (LD)
83468347
DAG.makeEquivalentMemoryOrdering(LD, NewLd);
@@ -8427,7 +8428,7 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
84278428
SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
84288429
SDValue ResNode = DAG.getMemIntrinsicNode(
84298430
X86ISD::VZEXT_LOAD, DL, Tys, Ops, VecSVT, LDBase->getPointerInfo(),
8430-
LDBase->getAlign(), MachineMemOperand::MOLoad);
8431+
LDBase->getOriginalAlign(), MachineMemOperand::MOLoad);
84318432
for (auto *LD : Loads)
84328433
if (LD)
84338434
DAG.makeEquivalentMemoryOrdering(LD, ResNode);
@@ -8669,7 +8670,7 @@ static SDValue lowerBuildVectorAsBroadcast(BuildVectorSDNode *BVOp,
86698670
SDValue CP = DAG.getConstantPool(C, PVT);
86708671
unsigned Repeat = VT.getSizeInBits() / SplatBitSize;
86718672

8672-
MaybeAlign Alignment(cast<ConstantPoolSDNode>(CP)->getAlignment());
8673+
Align Alignment(cast<ConstantPoolSDNode>(CP)->getAlignment());
86738674
SDVTList Tys =
86748675
DAG.getVTList(MVT::getVectorVT(CVT, Repeat), MVT::Other);
86758676
SDValue Ops[] = {DAG.getEntryNode(), CP};
@@ -8687,7 +8688,7 @@ static SDValue lowerBuildVectorAsBroadcast(BuildVectorSDNode *BVOp,
86878688
*Ctx);
86888689
SDValue VCP = DAG.getConstantPool(VecC, PVT);
86898690
unsigned NumElm = SplatBitSize / VT.getScalarSizeInBits();
8690-
unsigned Alignment = cast<ConstantPoolSDNode>(VCP)->getAlignment();
8691+
Align Alignment(cast<ConstantPoolSDNode>(VCP)->getAlignment());
86918692
Ld = DAG.getLoad(
86928693
MVT::getVectorVT(CVT, NumElm), dl, DAG.getEntryNode(), VCP,
86938694
MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
@@ -8757,7 +8758,7 @@ static SDValue lowerBuildVectorAsBroadcast(BuildVectorSDNode *BVOp,
87578758
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
87588759
SDValue CP =
87598760
DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
8760-
MaybeAlign Alignment(cast<ConstantPoolSDNode>(CP)->getAlignment());
8761+
Align Alignment(cast<ConstantPoolSDNode>(CP)->getAlignment());
87618762

87628763
SDVTList Tys = DAG.getVTList(VT, MVT::Other);
87638764
SDValue Ops[] = {DAG.getEntryNode(), CP};
@@ -19885,7 +19886,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
1988519886
APInt FF(64, 0x5F80000000000000ULL);
1988619887
SDValue FudgePtr = DAG.getConstantPool(
1988719888
ConstantInt::get(*DAG.getContext(), FF), PtrVT);
19888-
unsigned CPAlignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
19889+
Align CPAlignment(cast<ConstantPoolSDNode>(FudgePtr)->getAlignment());
1988919890

1989019891
// Get a pointer to FF if the sign bit was set, or to 0 otherwise.
1989119892
SDValue Zero = DAG.getIntPtrConstant(0, dl);
@@ -23229,16 +23230,16 @@ static SDValue splitVectorStore(StoreSDNode *Store, SelectionDAG &DAG) {
2322923230
SDLoc DL(Store);
2323023231
SDValue Value0, Value1;
2323123232
std::tie(Value0, Value1) = splitVector(StoredVal, DAG, DL);
23232-
unsigned HalfAlign = (StoredVal.getValueType().is256BitVector() ? 16 : 32);
23233+
unsigned HalfOffset = Value0.getValueType().getStoreSize();
2323323234
SDValue Ptr0 = Store->getBasePtr();
23234-
SDValue Ptr1 = DAG.getMemBasePlusOffset(Ptr0, HalfAlign, DL);
23235-
unsigned Alignment = Store->getAlignment();
23235+
SDValue Ptr1 = DAG.getMemBasePlusOffset(Ptr0, HalfOffset, DL);
2323623236
SDValue Ch0 =
2323723237
DAG.getStore(Store->getChain(), DL, Value0, Ptr0, Store->getPointerInfo(),
23238-
Alignment, Store->getMemOperand()->getFlags());
23238+
Store->getOriginalAlign(),
23239+
Store->getMemOperand()->getFlags());
2323923240
SDValue Ch1 = DAG.getStore(Store->getChain(), DL, Value1, Ptr1,
23240-
Store->getPointerInfo().getWithOffset(HalfAlign),
23241-
MinAlign(Alignment, HalfAlign),
23241+
Store->getPointerInfo().getWithOffset(HalfOffset),
23242+
Store->getOriginalAlign(),
2324223243
Store->getMemOperand()->getFlags());
2324323244
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Ch0, Ch1);
2324423245
}
@@ -23261,7 +23262,6 @@ static SDValue scalarizeVectorStore(StoreSDNode *Store, MVT StoreVT,
2326123262
MVT StoreSVT = StoreVT.getScalarType();
2326223263
unsigned NumElems = StoreVT.getVectorNumElements();
2326323264
unsigned ScalarSize = StoreSVT.getStoreSize();
23264-
unsigned Alignment = Store->getAlignment();
2326523265

2326623266
SDLoc DL(Store);
2326723267
SmallVector<SDValue, 4> Stores;
@@ -23272,7 +23272,7 @@ static SDValue scalarizeVectorStore(StoreSDNode *Store, MVT StoreVT,
2327223272
DAG.getIntPtrConstant(i, DL));
2327323273
SDValue Ch = DAG.getStore(Store->getChain(), DL, Scl, Ptr,
2327423274
Store->getPointerInfo().getWithOffset(Offset),
23275-
MinAlign(Alignment, Offset),
23275+
Store->getOriginalAlign(),
2327623276
Store->getMemOperand()->getFlags());
2327723277
Stores.push_back(Ch);
2327823278
}
@@ -23301,7 +23301,7 @@ static SDValue LowerStore(SDValue Op, const X86Subtarget &Subtarget,
2330123301
StoredVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, StoredVal);
2330223302

2330323303
return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
23304-
St->getPointerInfo(), St->getAlignment(),
23304+
St->getPointerInfo(), St->getOriginalAlign(),
2330523305
St->getMemOperand()->getFlags());
2330623306
}
2330723307

@@ -23342,7 +23342,7 @@ static SDValue LowerStore(SDValue Op, const X86Subtarget &Subtarget,
2334223342
DAG.getIntPtrConstant(0, dl));
2334323343

2334423344
return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
23345-
St->getPointerInfo(), St->getAlignment(),
23345+
St->getPointerInfo(), St->getOriginalAlign(),
2334623346
St->getMemOperand()->getFlags());
2334723347
}
2334823348
assert(Subtarget.hasSSE1() && "Expected SSE");
@@ -23377,7 +23377,7 @@ static SDValue LowerLoad(SDValue Op, const X86Subtarget &Subtarget,
2337723377
"Expected AVX512F without AVX512DQI");
2337823378

2337923379
SDValue NewLd = DAG.getLoad(MVT::i8, dl, Ld->getChain(), Ld->getBasePtr(),
23380-
Ld->getPointerInfo(), Ld->getAlignment(),
23380+
Ld->getPointerInfo(), Ld->getOriginalAlign(),
2338123381
Ld->getMemOperand()->getFlags());
2338223382

2338323383
// Replace chain users with the new chain.
@@ -30019,7 +30019,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3001930019
if (Subtarget.hasSSE2()) {
3002030020
MVT LdVT = Subtarget.is64Bit() && VT.isInteger() ? MVT::i64 : MVT::f64;
3002130021
SDValue Res = DAG.getLoad(LdVT, dl, Ld->getChain(), Ld->getBasePtr(),
30022-
Ld->getPointerInfo(), Ld->getAlignment(),
30022+
Ld->getPointerInfo(), Ld->getOriginalAlign(),
3002330023
Ld->getMemOperand()->getFlags());
3002430024
SDValue Chain = Res.getValue(1);
3002530025
MVT VecVT = MVT::getVectorVT(LdVT, 2);
@@ -35470,7 +35470,7 @@ static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG,
3547035470
SDValue Ops[] = { LN->getChain(), LN->getBasePtr() };
3547135471
SDValue VZLoad = DAG.getMemIntrinsicNode(
3547235472
X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::f64, LN->getPointerInfo(),
35473-
LN->getAlign(), LN->getMemOperand()->getFlags());
35473+
LN->getOriginalAlign(), LN->getMemOperand()->getFlags());
3547435474
SDValue Movddup = DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, VZLoad);
3547535475
DCI.CombineTo(N.getNode(), Movddup);
3547635476
DAG.ReplaceAllUsesOfValueWith(SDValue(LN, 1), VZLoad.getValue(1));
@@ -35570,7 +35570,7 @@ static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG,
3557035570
SDValue Ops[] = { LN->getChain(), LN->getBasePtr() };
3557135571
SDValue BcastLd = DAG.getMemIntrinsicNode(
3557235572
X86ISD::VBROADCAST_LOAD, DL, Tys, Ops, MVT::i16,
35573-
LN->getPointerInfo(), LN->getAlign(),
35573+
LN->getPointerInfo(), LN->getOriginalAlign(),
3557435574
LN->getMemOperand()->getFlags());
3557535575
DCI.CombineTo(N.getNode(), BcastLd);
3557635576
DAG.ReplaceAllUsesOfValueWith(SDValue(LN, 1), BcastLd.getValue(1));
@@ -35615,7 +35615,7 @@ static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG,
3561535615
SDValue BcastLd = DAG.getMemIntrinsicNode(
3561635616
X86ISD::VBROADCAST_LOAD, DL, Tys, Ops, MVT::i16,
3561735617
LN->getPointerInfo().getWithOffset(Offset),
35618-
commonAlignment(LN->getAlign(), Offset),
35618+
LN->getOriginalAlign(),
3561935619
LN->getMemOperand()->getFlags());
3562035620
DCI.CombineTo(N.getNode(), BcastLd);
3562135621
DAG.ReplaceAllUsesOfValueWith(SDValue(LN, 1), BcastLd.getValue(1));
@@ -38314,7 +38314,7 @@ static SDValue combineExtractWithShuffle(SDNode *N, SelectionDAG &DAG,
3831438314
SDValue Load = DAG.getLoad(VT, dl, MemIntr->getChain(),
3831538315
MemIntr->getBasePtr(),
3831638316
MemIntr->getPointerInfo(),
38317-
MemIntr->getAlignment(),
38317+
MemIntr->getOriginalAlign(),
3831838318
MemIntr->getMemOperand()->getFlags());
3831938319
DAG.ReplaceAllUsesOfValueWith(SDValue(MemIntr, 1), Load.getValue(1));
3832038320
return Load;
@@ -42578,28 +42578,29 @@ static SDValue combineLoad(SDNode *N, SelectionDAG &DAG,
4257842578
// pre-AVX2 targets as 32-byte loads will lower to regular temporal loads.
4257942579
ISD::LoadExtType Ext = Ld->getExtensionType();
4258042580
bool Fast;
42581-
unsigned Alignment = Ld->getAlignment();
4258242581
if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
4258342582
Ext == ISD::NON_EXTLOAD &&
42584-
((Ld->isNonTemporal() && !Subtarget.hasInt256() && Alignment >= 16) ||
42583+
((Ld->isNonTemporal() && !Subtarget.hasInt256() &&
42584+
Ld->getAlignment() >= 16) ||
4258542585
(TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
4258642586
*Ld->getMemOperand(), &Fast) &&
4258742587
!Fast))) {
4258842588
unsigned NumElems = RegVT.getVectorNumElements();
4258942589
if (NumElems < 2)
4259042590
return SDValue();
4259142591

42592-
unsigned HalfAlign = 16;
42592+
unsigned HalfOffset = 16;
4259342593
SDValue Ptr1 = Ld->getBasePtr();
42594-
SDValue Ptr2 = DAG.getMemBasePlusOffset(Ptr1, HalfAlign, dl);
42594+
SDValue Ptr2 = DAG.getMemBasePlusOffset(Ptr1, HalfOffset, dl);
4259542595
EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
4259642596
NumElems / 2);
4259742597
SDValue Load1 =
4259842598
DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr1, Ld->getPointerInfo(),
42599-
Alignment, Ld->getMemOperand()->getFlags());
42599+
Ld->getOriginalAlign(),
42600+
Ld->getMemOperand()->getFlags());
4260042601
SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr2,
42601-
Ld->getPointerInfo().getWithOffset(HalfAlign),
42602-
MinAlign(Alignment, HalfAlign),
42602+
Ld->getPointerInfo().getWithOffset(HalfOffset),
42603+
Ld->getOriginalAlign(),
4260342604
Ld->getMemOperand()->getFlags());
4260442605
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4260542606
Load1.getValue(1), Load2.getValue(1));
@@ -42616,7 +42617,8 @@ static SDValue combineLoad(SDNode *N, SelectionDAG &DAG,
4261642617
EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumElts);
4261742618
if (TLI.isTypeLegal(IntVT)) {
4261842619
SDValue IntLoad = DAG.getLoad(IntVT, dl, Ld->getChain(), Ld->getBasePtr(),
42619-
Ld->getPointerInfo(), Alignment,
42620+
Ld->getPointerInfo(),
42621+
Ld->getOriginalAlign(),
4262042622
Ld->getMemOperand()->getFlags());
4262142623
SDValue BoolVec = DAG.getBitcast(RegVT, IntLoad);
4262242624
return DCI.CombineTo(N, BoolVec, IntLoad.getValue(1), true);
@@ -42868,7 +42870,6 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
4286842870
StoreSDNode *St = cast<StoreSDNode>(N);
4286942871
EVT StVT = St->getMemoryVT();
4287042872
SDLoc dl(St);
42871-
unsigned Alignment = St->getAlignment();
4287242873
SDValue StoredVal = St->getValue();
4287342874
EVT VT = StoredVal.getValueType();
4287442875
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
@@ -42881,7 +42882,7 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
4288142882
StoredVal = DAG.getBitcast(NewVT, StoredVal);
4288242883

4288342884
return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
42884-
St->getPointerInfo(), St->getAlignment(),
42885+
St->getPointerInfo(), St->getOriginalAlign(),
4288542886
St->getMemOperand()->getFlags());
4288642887
}
4288742888

@@ -42892,7 +42893,8 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
4289242893
StoredVal.getOperand(0).getValueType() == MVT::i8) {
4289342894
return DAG.getStore(St->getChain(), dl, StoredVal.getOperand(0),
4289442895
St->getBasePtr(), St->getPointerInfo(),
42895-
St->getAlignment(), St->getMemOperand()->getFlags());
42896+
St->getOriginalAlign(),
42897+
St->getMemOperand()->getFlags());
4289642898
}
4289742899

4289842900
// Widen v2i1/v4i1 stores to v8i1.
@@ -42903,7 +42905,7 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
4290342905
Ops[0] = StoredVal;
4290442906
StoredVal = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
4290542907
return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
42906-
St->getPointerInfo(), St->getAlignment(),
42908+
St->getPointerInfo(), St->getOriginalAlign(),
4290742909
St->getMemOperand()->getFlags());
4290842910
}
4290942911

@@ -42925,18 +42927,19 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
4292542927

4292642928
SDValue Ch0 =
4292742929
DAG.getStore(St->getChain(), dl, Lo, Ptr0, St->getPointerInfo(),
42928-
Alignment, St->getMemOperand()->getFlags());
42930+
St->getOriginalAlign(),
42931+
St->getMemOperand()->getFlags());
4292942932
SDValue Ch1 =
4293042933
DAG.getStore(St->getChain(), dl, Hi, Ptr1,
4293142934
St->getPointerInfo().getWithOffset(4),
42932-
MinAlign(Alignment, 4U),
42935+
St->getOriginalAlign(),
4293342936
St->getMemOperand()->getFlags());
4293442937
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
4293542938
}
4293642939

4293742940
StoredVal = combinevXi1ConstantToInteger(StoredVal, DAG);
4293842941
return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
42939-
St->getPointerInfo(), St->getAlignment(),
42942+
St->getPointerInfo(), St->getOriginalAlign(),
4294042943
St->getMemOperand()->getFlags());
4294142944
}
4294242945

@@ -42955,7 +42958,8 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
4295542958
}
4295642959

4295742960
// Split under-aligned vector non-temporal stores.
42958-
if (St->isNonTemporal() && StVT == VT && Alignment < VT.getStoreSize()) {
42961+
if (St->isNonTemporal() && StVT == VT &&
42962+
St->getAlignment() < VT.getStoreSize()) {
4295942963
// ZMM/YMM nt-stores - either it can be stored as a series of shorter
4296042964
// vectors or the legalizer can scalarize it to use MOVNTI.
4296142965
if (VT.is256BitVector() || VT.is512BitVector()) {
@@ -43009,7 +43013,7 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
4300943013
if (SDValue Avg = detectAVGPattern(St->getValue(), St->getMemoryVT(), DAG,
4301043014
Subtarget, dl))
4301143015
return DAG.getStore(St->getChain(), dl, Avg, St->getBasePtr(),
43012-
St->getPointerInfo(), St->getAlignment(),
43016+
St->getPointerInfo(), St->getOriginalAlign(),
4301343017
St->getMemOperand()->getFlags());
4301443018

4301543019
if (TLI.isTruncStoreLegal(VT, StVT)) {
@@ -43081,7 +43085,7 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
4308143085
SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4308243086
BitCast, OldExtract.getOperand(1));
4308343087
return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
43084-
St->getPointerInfo(), St->getAlignment(),
43088+
St->getPointerInfo(), St->getOriginalAlign(),
4308543089
St->getMemOperand()->getFlags());
4308643090
}
4308743091

@@ -44372,7 +44376,7 @@ static SDValue combineX86INT_TO_FP(SDNode *N, SelectionDAG &DAG,
4437244376
SDValue Ops[] = { LN->getChain(), LN->getBasePtr() };
4437344377
SDValue VZLoad = DAG.getMemIntrinsicNode(
4437444378
X86ISD::VZEXT_LOAD, dl, Tys, Ops, MemVT, LN->getPointerInfo(),
44375-
LN->getAlign(), LN->getMemOperand()->getFlags());
44379+
LN->getOriginalAlign(), LN->getMemOperand()->getFlags());
4437644380
SDValue Convert = DAG.getNode(N->getOpcode(), dl, VT,
4437744381
DAG.getBitcast(InVT, VZLoad));
4437844382
DCI.CombineTo(N, Convert);
@@ -44406,7 +44410,7 @@ static SDValue combineCVTP2I_CVTTP2I(SDNode *N, SelectionDAG &DAG,
4440644410
SDValue Ops[] = { LN->getChain(), LN->getBasePtr() };
4440744411
SDValue VZLoad = DAG.getMemIntrinsicNode(
4440844412
X86ISD::VZEXT_LOAD, dl, Tys, Ops, MemVT, LN->getPointerInfo(),
44409-
LN->getAlign(), LN->getMemOperand()->getFlags());
44413+
LN->getOriginalAlign(), LN->getMemOperand()->getFlags());
4441044414
SDValue Convert = DAG.getNode(N->getOpcode(), dl, VT,
4441144415
DAG.getBitcast(InVT, VZLoad));
4441244416
DCI.CombineTo(N, Convert);
@@ -44493,7 +44497,7 @@ static SDValue combineCVTPH2PS(SDNode *N, SelectionDAG &DAG,
4449344497
SDValue Ops[] = { LN->getChain(), LN->getBasePtr() };
4449444498
SDValue VZLoad = DAG.getMemIntrinsicNode(
4449544499
X86ISD::VZEXT_LOAD, dl, Tys, Ops, MVT::i64, LN->getPointerInfo(),
44496-
LN->getAlign(), LN->getMemOperand()->getFlags());
44500+
LN->getOriginalAlign(), LN->getMemOperand()->getFlags());
4449744501
SDValue Convert = DAG.getNode(N->getOpcode(), dl, MVT::v4f32,
4449844502
DAG.getBitcast(MVT::v8i16, VZLoad));
4449944503
DCI.CombineTo(N, Convert);
@@ -45735,7 +45739,7 @@ static SDValue combineSIntToFP(SDNode *N, SelectionDAG &DAG,
4573545739
std::pair<SDValue, SDValue> Tmp =
4573645740
Subtarget.getTargetLowering()->BuildFILD(
4573745741
VT, InVT, SDLoc(N), Ld->getChain(), Ld->getBasePtr(),
45738-
Ld->getPointerInfo(), Ld->getAlign(), DAG);
45742+
Ld->getPointerInfo(), Ld->getOriginalAlign(), DAG);
4573945743
DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), Tmp.second);
4574045744
return Tmp.first;
4574145745
}
@@ -47257,7 +47261,8 @@ static SDValue combineExtInVec(SDNode *N, SelectionDAG &DAG,
4725747261
if (TLI.isLoadExtLegal(Ext, VT, MemVT)) {
4725847262
SDValue Load =
4725947263
DAG.getExtLoad(Ext, SDLoc(N), VT, Ld->getChain(), Ld->getBasePtr(),
47260-
Ld->getPointerInfo(), MemVT, Ld->getAlignment(),
47264+
Ld->getPointerInfo(), MemVT,
47265+
Ld->getOriginalAlign(),
4726147266
Ld->getMemOperand()->getFlags());
4726247267
DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
4726347268
return Load;

‎llvm/test/CodeGen/X86/merge-consecutive-stores-nt.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -48,10 +48,10 @@ define void @merge_2_v4f32_align32(<4 x float>* %a0, <4 x float>* %a1) nounwind
4848
;
4949
; X64-AVX1-LABEL: merge_2_v4f32_align32:
5050
; X64-AVX1: # %bb.0:
51-
; X64-AVX1-NEXT: vmovntdqa (%rdi), %xmm0
52-
; X64-AVX1-NEXT: vmovntdqa 16(%rdi), %xmm1
53-
; X64-AVX1-NEXT: vmovntdq %xmm1, 16(%rsi)
54-
; X64-AVX1-NEXT: vmovntdq %xmm0, (%rsi)
51+
; X64-AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0
52+
; X64-AVX1-NEXT: vmovntdqa (%rdi), %xmm1
53+
; X64-AVX1-NEXT: vmovntdq %xmm1, (%rsi)
54+
; X64-AVX1-NEXT: vmovntdq %xmm0, 16(%rsi)
5555
; X64-AVX1-NEXT: retq
5656
;
5757
; X64-AVX2-LABEL: merge_2_v4f32_align32:

0 commit comments

Comments
 (0)