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[LLVM][AARCH64]Replace +sme2p1+smef16f16 by +smef16f16
According to the latest ISA Spec release[1] all instructions under: HasSME2p1 and HasSMEF16F16 should now only require: HasSMEF16F16 [1]https://developer.arm.com
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18 files changed

+479
-476
lines changed

18 files changed

+479
-476
lines changed

‎llvm/include/llvm/TargetParser/AArch64TargetParser.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -302,7 +302,7 @@ inline constexpr ExtensionInfo Extensions[] = {
302302
{"ssve-fp8dot4", AArch64::AEK_SSVE_FP8DOT4, "+ssve-fp8dot4", "-ssve-fp8dot4", FEAT_INIT, "+sme2", 0},
303303
{"lut", AArch64::AEK_LUT, "+lut", "-lut", FEAT_INIT, "", 0},
304304
{"sme-lutv2", AArch64::AEK_SME_LUTv2, "+sme-lutv2", "-sme-lutv2", FEAT_INIT, "", 0},
305-
{"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16", FEAT_INIT, "+sme2,+fp8", 0},
305+
{"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16", FEAT_INIT, "+sme2,+fp8,+sme-f16f16", 0},
306306
{"sme-f8f32", AArch64::AEK_SMEF8F32, "+sme-f8f32", "-sme-f8f32", FEAT_INIT, "+sme2,+fp8", 0},
307307
{"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64", FEAT_INIT, "", 0},
308308
{"cpa", AArch64::AEK_CPA, "+cpa", "-cpa", FEAT_INIT, "", 0},

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -554,7 +554,7 @@ def FeatureSME_LUTv2 : SubtargetFeature<"sme-lutv2", "HasSME_LUTv2", "true",
554554
"Enable Scalable Matrix Extension (SME) LUTv2 instructions (FEAT_SME_LUTv2)">;
555555

556556
def FeatureSMEF8F16 : SubtargetFeature<"sme-f8f16", "HasSMEF8F16", "true",
557-
"Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSME2, FeatureFP8]>;
557+
"Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSME2, FeatureFP8, FeatureSMEF16F16]>;
558558

559559
def FeatureSMEF8F32 : SubtargetFeature<"sme-f8f32", "HasSMEF8F32", "true",
560560
"Enable Scalable Matrix Extension (SME) F8F32 instructions (FEAT_SME_F8F32)", [FeatureSME2, FeatureFP8]>;

‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -792,7 +792,7 @@ defm LUTI4_S_2ZTZI : sme2p1_luti4_vector_vg2_index<"luti4">;
792792
defm LUTI4_S_4ZTZI : sme2p1_luti4_vector_vg4_index<"luti4">;
793793
}
794794

795-
let Predicates = [HasSME2p1, HasSMEF16F16] in {
795+
let Predicates = [HasSMEF16F16] in {
796796
defm FADD_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fadd", 0b0100, MatrixOp16, ZZ_h_mul_r, nxv8f16, null_frag>;
797797
defm FADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fadd", 0b0100, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>;
798798
defm FSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fsub", 0b0101, MatrixOp16, ZZ_h_mul_r, nxv8f16, null_frag>;

‎llvm/test/MC/AArch64/SME2p1/fadd-diagnostics.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 2>&1 < %s | FileCheck %s
22

33
// --------------------------------------------------------------------------//
44
// Out of range index offset

‎llvm/test/MC/AArch64/SME2p1/fadd.s

Lines changed: 56 additions & 54 deletions
Large diffs are not rendered by default.

‎llvm/test/MC/AArch64/SME2p1/fcvt.s

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,36 +1,36 @@
1-
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
22
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
33
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
44
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5-
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
6-
// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST
7-
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
6+
// RUN: | llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
88
// RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9-
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
9+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
1010
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
11-
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \
11+
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble -show-encoding \
1212
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
1313

1414
fcvt {z0.s, z1.s}, z0.h // 11000001-10100000-11100000-00000000
1515
// CHECK-INST: fcvt { z0.s, z1.s }, z0.h
1616
// CHECK-ENCODING: [0x00,0xe0,0xa0,0xc1]
17-
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
17+
// CHECK-ERROR: instruction requires: sme-f16f16
1818
// CHECK-UNKNOWN: c1a0e000 <unknown>
1919

2020
fcvt {z20.s, z21.s}, z10.h // 11000001-10100000-11100001-01010100
2121
// CHECK-INST: fcvt { z20.s, z21.s }, z10.h
2222
// CHECK-ENCODING: [0x54,0xe1,0xa0,0xc1]
23-
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
23+
// CHECK-ERROR: instruction requires: sme-f16f16
2424
// CHECK-UNKNOWN: c1a0e154 <unknown>
2525

2626
fcvt {z22.s, z23.s}, z13.h // 11000001-10100000-11100001-10110110
2727
// CHECK-INST: fcvt { z22.s, z23.s }, z13.h
2828
// CHECK-ENCODING: [0xb6,0xe1,0xa0,0xc1]
29-
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
29+
// CHECK-ERROR: instruction requires: sme-f16f16
3030
// CHECK-UNKNOWN: c1a0e1b6 <unknown>
3131

3232
fcvt {z30.s, z31.s}, z31.h // 11000001-10100000-11100011-11111110
3333
// CHECK-INST: fcvt { z30.s, z31.s }, z31.h
3434
// CHECK-ENCODING: [0xfe,0xe3,0xa0,0xc1]
35-
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
35+
// CHECK-ERROR: instruction requires: sme-f16f16
3636
// CHECK-UNKNOWN: c1a0e3fe <unknown>

‎llvm/test/MC/AArch64/SME2p1/fcvtl-diagnostics.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 2>&1 < %s | FileCheck %s
22

33
// --------------------------------------------------------------------------//
44
// Invalid vector list

‎llvm/test/MC/AArch64/SME2p1/fcvtl.s

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,36 +1,36 @@
1-
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
22
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
33
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
44
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5-
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
6-
// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST
7-
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
6+
// RUN: | llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
88
// RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9-
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
9+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
1010
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
11-
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \
11+
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble -show-encoding \
1212
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
1313

1414
fcvtl {z0.s, z1.s}, z0.h // 11000001-10100000-11100000-00000001
1515
// CHECK-INST: fcvtl { z0.s, z1.s }, z0.h
1616
// CHECK-ENCODING: [0x01,0xe0,0xa0,0xc1]
17-
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
17+
// CHECK-ERROR: instruction requires: sme-f16f16
1818
// CHECK-UNKNOWN: c1a0e001 <unknown>
1919

2020
fcvtl {z20.s, z21.s}, z10.h // 11000001-10100000-11100001-01010101
2121
// CHECK-INST: fcvtl { z20.s, z21.s }, z10.h
2222
// CHECK-ENCODING: [0x55,0xe1,0xa0,0xc1]
23-
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
23+
// CHECK-ERROR: instruction requires: sme-f16f16
2424
// CHECK-UNKNOWN: c1a0e155 <unknown>
2525

2626
fcvtl {z22.s, z23.s}, z13.h // 11000001-10100000-11100001-10110111
2727
// CHECK-INST: fcvtl { z22.s, z23.s }, z13.h
2828
// CHECK-ENCODING: [0xb7,0xe1,0xa0,0xc1]
29-
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
29+
// CHECK-ERROR: instruction requires: sme-f16f16
3030
// CHECK-UNKNOWN: c1a0e1b7 <unknown>
3131

3232
fcvtl {z30.s, z31.s}, z31.h // 11000001-10100000-11100011-11111111
3333
// CHECK-INST: fcvtl { z30.s, z31.s }, z31.h
3434
// CHECK-ENCODING: [0xff,0xe3,0xa0,0xc1]
35-
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
35+
// CHECK-ERROR: instruction requires: sme-f16f16
3636
// CHECK-UNKNOWN: c1a0e3ff <unknown>

‎llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 2>&1 < %s | FileCheck %s
22

33
// --------------------------------------------------------------------------//
44
// Invalid vector list
@@ -66,7 +66,7 @@ fmla za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
6666
// Invalid Register Suffix
6767

6868
fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
69-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
69+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .h
7070
// CHECK-NEXT: fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
7171
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
7272

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