[DAG] SimplifySetCC - relax fold (X^C1) == C2 --> X == C1^C2

https://alive2.llvm.org/ce/z/A_auBq

Remove limitation that wouldn't perform the fold if all the inverted bits are known zero

The thumb2 changes look to be benign, although it does show that the TEQ/TST isel patterns could probably be improved.

Fixes movmsk regression in D122754

Differential Revision: https://reviews.llvm.org/D123023

Author: RKSimon

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -4649,11 +4649,8 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
                                 dl, N0.getValueType()),
                 Cond);
 
-          // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
-          // If we know that all of the inverted bits are zero, don't bother
-          // performing the inversion.
-          if (N0.getOpcode() == ISD::XOR &&
-              DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
+          // Turn (X^C1) == C2 --> X == C1^C2
+          if (N0.getOpcode() == ISD::XOR && N0.getNode()->hasOneUse())
             return DAG.getSetCC(
                 dl, VT, N0.getOperand(0),
                 DAG.getConstant(LHSR->getAPIntValue() ^ RHSC->getAPIntValue(),

llvm/test/CodeGen/Mips/countleading.ll

@@ -198,8 +198,7 @@ declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
 define i64 @ctlo_i64(i64 %X) nounwind readnone {
 ; MIPS32-R1-R2-LABEL: ctlo_i64:
 ; MIPS32-R1-R2:       # %bb.0: # %entry
-; MIPS32-R1-R2-NEXT:    addiu $1, $zero, -1
-; MIPS32-R1-R2-NEXT:    xor $1, $5, $1
+; MIPS32-R1-R2-NEXT:    not $1, $5
 ; MIPS32-R1-R2-NEXT:    clo $3, $5
 ; MIPS32-R1-R2-NEXT:    clo $2, $4
 ; MIPS32-R1-R2-NEXT:    addiu $2, $2, 32
@@ -209,15 +208,13 @@ define i64 @ctlo_i64(i64 %X) nounwind readnone {
 ;
 ; MIPS32-R6-LABEL: ctlo_i64:
 ; MIPS32-R6:       # %bb.0: # %entry
-; MIPS32-R6-NEXT:    addiu $1, $zero, -1
-; MIPS32-R6-NEXT:    xor $1, $5, $1
-; MIPS32-R6-NEXT:    sltu $1, $zero, $1
-; MIPS32-R6-NEXT:    clo $2, $4
-; MIPS32-R6-NEXT:    addiu $2, $2, 32
-; MIPS32-R6-NEXT:    seleqz $2, $2, $1
-; MIPS32-R6-NEXT:    clo $3, $5
-; MIPS32-R6-NEXT:    selnez $1, $3, $1
-; MIPS32-R6-NEXT:    or $2, $1, $2
+; MIPS32-R6-NEXT:    not $1, $5
+; MIPS32-R6-NEXT:    clo $2, $5
+; MIPS32-R6-NEXT:    selnez $2, $2, $1
+; MIPS32-R6-NEXT:    clo $3, $4
+; MIPS32-R6-NEXT:    addiu $3, $3, 32
+; MIPS32-R6-NEXT:    seleqz $1, $3, $1
+; MIPS32-R6-NEXT:    or $2, $2, $1
 ; MIPS32-R6-NEXT:    jr $ra
 ; MIPS32-R6-NEXT:    addiu $3, $zero, 0
 ;

llvm/test/CodeGen/Thumb2/thumb2-teq.ll

@@ -9,7 +9,7 @@ define i32 @f2(i32 %a) {
 ; CHECK-LABEL: f2:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    movs r1, #24
-; CHECK-NEXT:    teq.w r0, #187
+; CHECK-NEXT:    cmp r0, #187
 ; CHECK-NEXT:    it eq
 ; CHECK-NEXT:    moveq r1, #42
 ; CHECK-NEXT:    mov r0, r1
@@ -25,7 +25,7 @@ define i32 @f3(i32 %a) {
 ; CHECK-LABEL: f3:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    movs r1, #24
-; CHECK-NEXT:    teq.w r0, #11141290
+; CHECK-NEXT:    cmp.w r0, #11141290
 ; CHECK-NEXT:    it eq
 ; CHECK-NEXT:    moveq r1, #42
 ; CHECK-NEXT:    mov r0, r1
@@ -41,7 +41,7 @@ define i32 @f6(i32 %a) {
 ; CHECK-LABEL: f6:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    movs r1, #24
-; CHECK-NEXT:    teq.w r0, #-872363008
+; CHECK-NEXT:    cmp.w r0, #-872363008
 ; CHECK-NEXT:    it eq
 ; CHECK-NEXT:    moveq r1, #42
 ; CHECK-NEXT:    mov r0, r1
@@ -57,7 +57,7 @@ define i32 @f7(i32 %a) {
 ; CHECK-LABEL: f7:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    movs r1, #24
-; CHECK-NEXT:    teq.w r0, #-572662307
+; CHECK-NEXT:    cmp.w r0, #-572662307
 ; CHECK-NEXT:    it eq
 ; CHECK-NEXT:    moveq r1, #42
 ; CHECK-NEXT:    mov r0, r1
@@ -73,7 +73,7 @@ define i32 @f10(i32 %a) {
 ; CHECK-LABEL: f10:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    movs r1, #24
-; CHECK-NEXT:    teq.w r0, #1114112
+; CHECK-NEXT:    cmp.w r0, #1114112
 ; CHECK-NEXT:    it eq
 ; CHECK-NEXT:    moveq r1, #42
 ; CHECK-NEXT:    mov r0, r1
@@ -88,7 +88,7 @@ define i32 @f10(i32 %a) {
 define i1 @f12(i32 %a) {
 ; CHECK-LABEL: f12:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    eor r0, r0, #187
+; CHECK-NEXT:    subs r0, #187
 ; CHECK-NEXT:    clz r0, r0
 ; CHECK-NEXT:    lsrs r0, r0, #5
 ; CHECK-NEXT:    bx lr
@@ -101,7 +101,7 @@ define i1 @f12(i32 %a) {
 define i1 @f13(i32 %a) {
 ; CHECK-LABEL: f13:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    eor r0, r0, #11141290
+; CHECK-NEXT:    sub.w r0, r0, #11141290
 ; CHECK-NEXT:    clz r0, r0
 ; CHECK-NEXT:    lsrs r0, r0, #5
 ; CHECK-NEXT:    bx lr
@@ -114,7 +114,7 @@ define i1 @f13(i32 %a) {
 define i1 @f16(i32 %a) {
 ; CHECK-LABEL: f16:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    eor r0, r0, #-872363008
+; CHECK-NEXT:    sub.w r0, r0, #-872363008
 ; CHECK-NEXT:    clz r0, r0
 ; CHECK-NEXT:    lsrs r0, r0, #5
 ; CHECK-NEXT:    bx lr
@@ -127,7 +127,7 @@ define i1 @f16(i32 %a) {
 define i1 @f17(i32 %a) {
 ; CHECK-LABEL: f17:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    eor r0, r0, #-572662307
+; CHECK-NEXT:    sub.w r0, r0, #-572662307
 ; CHECK-NEXT:    clz r0, r0
 ; CHECK-NEXT:    lsrs r0, r0, #5
 ; CHECK-NEXT:    bx lr
@@ -140,7 +140,7 @@ define i1 @f17(i32 %a) {
 define i1 @f18(i32 %a) {
 ; CHECK-LABEL: f18:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    eor r0, r0, #1114112
+; CHECK-NEXT:    sub.w r0, r0, #1114112
 ; CHECK-NEXT:    clz r0, r0
 ; CHECK-NEXT:    lsrs r0, r0, #5
 ; CHECK-NEXT:    bx lr

llvm/test/CodeGen/X86/peep-test-3.ll

@@ -41,7 +41,7 @@ define void @xor(float* %A, i32 %IA, i32 %N) nounwind {
 ; CHECK-NEXT:    movl %eax, %ecx
 ; CHECK-NEXT:    andl $3, %ecx
 ; CHECK-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
-; CHECK-NEXT:    xorl $1, %ecx
+; CHECK-NEXT:    cmpl $1, %ecx
 ; CHECK-NEXT:    je .LBB1_2
 ; CHECK-NEXT:  # %bb.1: # %bb
 ; CHECK-NEXT:    movl $0, (%eax)