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[GISel] Handle Flags in G_PTR_ADD Combines (#152495)
So far, GlobalISel's G_PTR_ADD combines have ignored MIFlags like nuw, nusw, and inbounds. That was in many cases unnecessarily conservative and in others unsound, since reassociations re-used the existing G_PTR_ADD instructions without invalidating their flags. This patch aims to improve that. I've checked the transforms in this PR with Alive2 on corresponding middle-end IR constructs. A longer-term goal would be to encapsulate the logic that determines which GEP/ISD::PTRADD/G_PTR_ADD flags can be preserved in which case, since this occurs in similar forms in the middle end, the SelectionDAG combines, and the GlobalISel combines here. For SWDEV-516125.
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‎llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,7 @@ struct PtrAddChain {
6666
int64_t Imm;
6767
Register Base;
6868
const RegisterBank *Bank;
69+
unsigned Flags;
6970
};
7071

7172
struct RegisterImmPair {

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp‎

Lines changed: 81 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1821,10 +1821,29 @@ bool CombinerHelper::matchPtrAddImmedChain(MachineInstr &MI,
18211821
return false;
18221822
}
18231823

1824+
// Reassociating nuw additions preserves nuw. If both original G_PTR_ADDs are
1825+
// inbounds, reaching the same result in one G_PTR_ADD is also inbounds.
1826+
// The nusw constraints are satisfied because imm1+imm2 cannot exceed the
1827+
// largest signed integer that fits into the index type, which is the maximum
1828+
// size of allocated objects according to the IR Language Reference.
1829+
unsigned PtrAddFlags = MI.getFlags();
1830+
unsigned LHSPtrAddFlags = Add2Def->getFlags();
1831+
bool IsNoUWrap = PtrAddFlags & LHSPtrAddFlags & MachineInstr::MIFlag::NoUWrap;
1832+
bool IsInBounds =
1833+
PtrAddFlags & LHSPtrAddFlags & MachineInstr::MIFlag::InBounds;
1834+
unsigned Flags = 0;
1835+
if (IsNoUWrap)
1836+
Flags |= MachineInstr::MIFlag::NoUWrap;
1837+
if (IsInBounds) {
1838+
Flags |= MachineInstr::MIFlag::InBounds;
1839+
Flags |= MachineInstr::MIFlag::NoUSWrap;
1840+
}
1841+
18241842
// Pass the combined immediate to the apply function.
18251843
MatchInfo.Imm = AMNew.BaseOffs;
18261844
MatchInfo.Base = Base;
18271845
MatchInfo.Bank = getRegBank(Imm2);
1846+
MatchInfo.Flags = Flags;
18281847
return true;
18291848
}
18301849

@@ -1838,6 +1857,7 @@ void CombinerHelper::applyPtrAddImmedChain(MachineInstr &MI,
18381857
Observer.changingInstr(MI);
18391858
MI.getOperand(1).setReg(MatchInfo.Base);
18401859
MI.getOperand(2).setReg(NewOffset.getReg(0));
1860+
MI.setFlags(MatchInfo.Flags);
18411861
Observer.changedInstr(MI);
18421862
}
18431863

@@ -4871,14 +4891,34 @@ bool CombinerHelper::matchReassocConstantInnerRHS(GPtrAdd &MI,
48714891
if (!C2)
48724892
return false;
48734893

4894+
// If both additions are nuw, the reassociated additions are also nuw.
4895+
// If the original G_PTR_ADD is additionally nusw, X and C are both not
4896+
// negative, so BASE+X is between BASE and BASE+(X+C). The new G_PTR_ADDs are
4897+
// therefore also nusw.
4898+
// If the original G_PTR_ADD is additionally inbounds (which implies nusw),
4899+
// the new G_PTR_ADDs are then also inbounds.
4900+
unsigned PtrAddFlags = MI.getFlags();
4901+
unsigned AddFlags = RHS->getFlags();
4902+
bool IsNoUWrap = PtrAddFlags & AddFlags & MachineInstr::MIFlag::NoUWrap;
4903+
bool IsNoUSWrap = IsNoUWrap && (PtrAddFlags & MachineInstr::MIFlag::NoUSWrap);
4904+
bool IsInBounds = IsNoUWrap && (PtrAddFlags & MachineInstr::MIFlag::InBounds);
4905+
unsigned Flags = 0;
4906+
if (IsNoUWrap)
4907+
Flags |= MachineInstr::MIFlag::NoUWrap;
4908+
if (IsNoUSWrap)
4909+
Flags |= MachineInstr::MIFlag::NoUSWrap;
4910+
if (IsInBounds)
4911+
Flags |= MachineInstr::MIFlag::InBounds;
4912+
48744913
MatchInfo = [=, &MI](MachineIRBuilder &B) {
48754914
LLT PtrTy = MRI.getType(MI.getOperand(0).getReg());
48764915

48774916
auto NewBase =
4878-
Builder.buildPtrAdd(PtrTy, Src1Reg, RHS->getOperand(1).getReg());
4917+
Builder.buildPtrAdd(PtrTy, Src1Reg, RHS->getOperand(1).getReg(), Flags);
48794918
Observer.changingInstr(MI);
48804919
MI.getOperand(1).setReg(NewBase.getReg(0));
48814920
MI.getOperand(2).setReg(RHS->getOperand(2).getReg());
4921+
MI.setFlags(Flags);
48824922
Observer.changedInstr(MI);
48834923
};
48844924
return !reassociationCanBreakAddressingModePattern(MI);
@@ -4897,6 +4937,25 @@ bool CombinerHelper::matchReassocConstantInnerLHS(GPtrAdd &MI,
48974937
return false;
48984938

48994939
auto *LHSPtrAdd = cast<GPtrAdd>(LHS);
4940+
4941+
// Reassociating nuw additions preserves nuw. If both original G_PTR_ADDs are
4942+
// nuw and inbounds (which implies nusw), the offsets are both non-negative,
4943+
// so the new G_PTR_ADDs are also inbounds.
4944+
unsigned PtrAddFlags = MI.getFlags();
4945+
unsigned LHSPtrAddFlags = LHSPtrAdd->getFlags();
4946+
bool IsNoUWrap = PtrAddFlags & LHSPtrAddFlags & MachineInstr::MIFlag::NoUWrap;
4947+
bool IsNoUSWrap = IsNoUWrap && (PtrAddFlags & LHSPtrAddFlags &
4948+
MachineInstr::MIFlag::NoUSWrap);
4949+
bool IsInBounds = IsNoUWrap && (PtrAddFlags & LHSPtrAddFlags &
4950+
MachineInstr::MIFlag::InBounds);
4951+
unsigned Flags = 0;
4952+
if (IsNoUWrap)
4953+
Flags |= MachineInstr::MIFlag::NoUWrap;
4954+
if (IsNoUSWrap)
4955+
Flags |= MachineInstr::MIFlag::NoUSWrap;
4956+
if (IsInBounds)
4957+
Flags |= MachineInstr::MIFlag::InBounds;
4958+
49004959
MatchInfo = [=, &MI](MachineIRBuilder &B) {
49014960
// When we change LHSPtrAdd's offset register we might cause it to use a reg
49024961
// before its def. Sink the instruction so the outer PTR_ADD to ensure this
@@ -4907,9 +4966,11 @@ bool CombinerHelper::matchReassocConstantInnerLHS(GPtrAdd &MI,
49074966
auto NewCst = B.buildConstant(MRI.getType(RHSReg), LHSCstOff->Value);
49084967
Observer.changingInstr(MI);
49094968
MI.getOperand(2).setReg(NewCst.getReg(0));
4969+
MI.setFlags(Flags);
49104970
Observer.changedInstr(MI);
49114971
Observer.changingInstr(*LHSPtrAdd);
49124972
LHSPtrAdd->getOperand(2).setReg(RHSReg);
4973+
LHSPtrAdd->setFlags(Flags);
49134974
Observer.changedInstr(*LHSPtrAdd);
49144975
};
49154976
return !reassociationCanBreakAddressingModePattern(MI);
@@ -4933,11 +4994,30 @@ bool CombinerHelper::matchReassocFoldConstantsInSubTree(
49334994
if (!C2)
49344995
return false;
49354996

4997+
// Reassociating nuw additions preserves nuw. If both original G_PTR_ADDs are
4998+
// inbounds, reaching the same result in one G_PTR_ADD is also inbounds.
4999+
// The nusw constraints are satisfied because imm1+imm2 cannot exceed the
5000+
// largest signed integer that fits into the index type, which is the maximum
5001+
// size of allocated objects according to the IR Language Reference.
5002+
unsigned PtrAddFlags = MI.getFlags();
5003+
unsigned LHSPtrAddFlags = LHSPtrAdd->getFlags();
5004+
bool IsNoUWrap = PtrAddFlags & LHSPtrAddFlags & MachineInstr::MIFlag::NoUWrap;
5005+
bool IsInBounds =
5006+
PtrAddFlags & LHSPtrAddFlags & MachineInstr::MIFlag::InBounds;
5007+
unsigned Flags = 0;
5008+
if (IsNoUWrap)
5009+
Flags |= MachineInstr::MIFlag::NoUWrap;
5010+
if (IsInBounds) {
5011+
Flags |= MachineInstr::MIFlag::InBounds;
5012+
Flags |= MachineInstr::MIFlag::NoUSWrap;
5013+
}
5014+
49365015
MatchInfo = [=, &MI](MachineIRBuilder &B) {
49375016
auto NewCst = B.buildConstant(MRI.getType(Src2Reg), *C1 + *C2);
49385017
Observer.changingInstr(MI);
49395018
MI.getOperand(1).setReg(LHSSrc1);
49405019
MI.getOperand(2).setReg(NewCst.getReg(0));
5020+
MI.setFlags(Flags);
49415021
Observer.changedInstr(MI);
49425022
};
49435023
return !reassociationCanBreakAddressingModePattern(MI);

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir‎

Lines changed: 242 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -320,3 +320,245 @@ body: |
320320
RET_ReallyLR
321321
322322
...
323+
---
324+
name: rhs_add_nuw
325+
alignment: 4
326+
liveins:
327+
- { reg: '$x0' }
328+
- { reg: '$x1' }
329+
body: |
330+
bb.1:
331+
liveins: $x0, $x1
332+
333+
; CHECK-LABEL: name: rhs_add_nuw
334+
; CHECK: liveins: $x0, $x1
335+
; CHECK-NEXT: {{ $}}
336+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
337+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
338+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
339+
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[COPY1]](s64)
340+
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD]], [[C]](s64)
341+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s8))
342+
; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
343+
; CHECK-NEXT: RET_ReallyLR implicit $w0
344+
%0:_(p0) = COPY $x0
345+
%1:_(s64) = COPY $x1
346+
%2:_(s64) = G_CONSTANT i64 1
347+
%3:_(s64) = nuw G_ADD %1, %2
348+
%4:_(p0) = nuw G_PTR_ADD %0, %3(s64)
349+
%7:_(s32) = G_LOAD %4(p0) :: (load 1)
350+
$w0 = COPY %7(s32)
351+
RET_ReallyLR implicit $w0
352+
353+
...
354+
---
355+
name: rhs_add_nuw_nusw
356+
alignment: 4
357+
liveins:
358+
- { reg: '$x0' }
359+
- { reg: '$x1' }
360+
body: |
361+
bb.1:
362+
liveins: $x0, $x1
363+
364+
; CHECK-LABEL: name: rhs_add_nuw_nusw
365+
; CHECK: liveins: $x0, $x1
366+
; CHECK-NEXT: {{ $}}
367+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
368+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
369+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
370+
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[COPY1]](s64)
371+
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD]], [[C]](s64)
372+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s8))
373+
; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
374+
; CHECK-NEXT: RET_ReallyLR implicit $w0
375+
%0:_(p0) = COPY $x0
376+
%1:_(s64) = COPY $x1
377+
%2:_(s64) = G_CONSTANT i64 1
378+
%3:_(s64) = nuw G_ADD %1, %2
379+
%4:_(p0) = nuw nusw G_PTR_ADD %0, %3(s64)
380+
%7:_(s32) = G_LOAD %4(p0) :: (load 1)
381+
$w0 = COPY %7(s32)
382+
RET_ReallyLR implicit $w0
383+
384+
...
385+
---
386+
name: rhs_add_nuw_inbounds
387+
alignment: 4
388+
liveins:
389+
- { reg: '$x0' }
390+
- { reg: '$x1' }
391+
body: |
392+
bb.1:
393+
liveins: $x0, $x1
394+
395+
; CHECK-LABEL: name: rhs_add_nuw_inbounds
396+
; CHECK: liveins: $x0, $x1
397+
; CHECK-NEXT: {{ $}}
398+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
399+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
400+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
401+
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[COPY1]](s64)
402+
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[C]](s64)
403+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s8))
404+
; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
405+
; CHECK-NEXT: RET_ReallyLR implicit $w0
406+
%0:_(p0) = COPY $x0
407+
%1:_(s64) = COPY $x1
408+
%2:_(s64) = G_CONSTANT i64 1
409+
%3:_(s64) = nuw G_ADD %1, %2
410+
%4:_(p0) = nuw nusw inbounds G_PTR_ADD %0, %3(s64)
411+
%7:_(s32) = G_LOAD %4(p0) :: (load 1)
412+
$w0 = COPY %7(s32)
413+
RET_ReallyLR implicit $w0
414+
415+
...
416+
---
417+
name: reassoc_nuw
418+
alignment: 4
419+
liveins:
420+
- { reg: '$x0' }
421+
- { reg: '$x1' }
422+
body: |
423+
bb.1:
424+
liveins: $x0, $x1
425+
426+
; CHECK-LABEL: name: reassoc_nuw
427+
; CHECK: liveins: $x0, $x1
428+
; CHECK-NEXT: {{ $}}
429+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
430+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
431+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
432+
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[COPY1]](s64)
433+
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD]], [[C]](s64)
434+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s8))
435+
; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
436+
; CHECK-NEXT: RET_ReallyLR implicit $w0
437+
%0:_(p0) = COPY $x0
438+
%1:_(s64) = COPY $x1
439+
%2:_(s64) = G_CONSTANT i64 1
440+
%3:_(p0) = nuw G_PTR_ADD %0, %2(s64)
441+
%4:_(p0) = nuw G_PTR_ADD %3(p0), %1
442+
%7:_(s32) = G_LOAD %4(p0) :: (load 1)
443+
$w0 = COPY %7(s32)
444+
RET_ReallyLR implicit $w0
445+
446+
...
447+
---
448+
name: reassoc_nuw_nusw
449+
alignment: 4
450+
liveins:
451+
- { reg: '$x0' }
452+
- { reg: '$x1' }
453+
body: |
454+
bb.1:
455+
liveins: $x0, $x1
456+
457+
; CHECK-LABEL: name: reassoc_nuw_nusw
458+
; CHECK: liveins: $x0, $x1
459+
; CHECK-NEXT: {{ $}}
460+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
461+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
462+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
463+
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[COPY1]](s64)
464+
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD]], [[C]](s64)
465+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s8))
466+
; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
467+
; CHECK-NEXT: RET_ReallyLR implicit $w0
468+
%0:_(p0) = COPY $x0
469+
%1:_(s64) = COPY $x1
470+
%2:_(s64) = G_CONSTANT i64 1
471+
%3:_(p0) = nuw nusw G_PTR_ADD %0, %2(s64)
472+
%4:_(p0) = nuw nusw G_PTR_ADD %3(p0), %1
473+
%7:_(s32) = G_LOAD %4(p0) :: (load 1)
474+
$w0 = COPY %7(s32)
475+
RET_ReallyLR implicit $w0
476+
477+
...
478+
---
479+
name: reassoc_nuw_inbounds
480+
alignment: 4
481+
liveins:
482+
- { reg: '$x0' }
483+
- { reg: '$x1' }
484+
body: |
485+
bb.1:
486+
liveins: $x0, $x1
487+
488+
; CHECK-LABEL: name: reassoc_nuw_inbounds
489+
; CHECK: liveins: $x0, $x1
490+
; CHECK-NEXT: {{ $}}
491+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
492+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
493+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
494+
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[COPY1]](s64)
495+
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[C]](s64)
496+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s8))
497+
; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
498+
; CHECK-NEXT: RET_ReallyLR implicit $w0
499+
%0:_(p0) = COPY $x0
500+
%1:_(s64) = COPY $x1
501+
%2:_(s64) = G_CONSTANT i64 1
502+
%3:_(p0) = nuw nusw inbounds G_PTR_ADD %0, %2(s64)
503+
%4:_(p0) = nuw nusw inbounds G_PTR_ADD %3(p0), %1
504+
%7:_(s32) = G_LOAD %4(p0) :: (load 1)
505+
$w0 = COPY %7(s32)
506+
RET_ReallyLR implicit $w0
507+
508+
...
509+
---
510+
name: combine_offsets_nuw
511+
alignment: 4
512+
liveins:
513+
- { reg: '$x0' }
514+
body: |
515+
bb.1:
516+
liveins: $x0
517+
518+
; CHECK-LABEL: name: combine_offsets_nuw
519+
; CHECK: liveins: $x0
520+
; CHECK-NEXT: {{ $}}
521+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
522+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 11
523+
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s64)
524+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s8))
525+
; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
526+
; CHECK-NEXT: RET_ReallyLR implicit $w0
527+
%0:_(p0) = COPY $x0
528+
%1:_(s64) = G_CONSTANT i64 10
529+
%2:_(s64) = G_CONSTANT i64 1
530+
%3:_(p0) = nuw G_PTR_ADD %0, %1
531+
%4:_(p0) = nuw G_PTR_ADD %3(p0), %2
532+
%7:_(s32) = G_LOAD %4(p0) :: (load 1)
533+
$w0 = COPY %7(s32)
534+
RET_ReallyLR implicit $w0
535+
536+
...
537+
---
538+
name: combine_offsets_nuw_inbounds
539+
alignment: 4
540+
liveins:
541+
- { reg: '$x0' }
542+
body: |
543+
bb.1:
544+
liveins: $x0
545+
546+
; CHECK-LABEL: name: combine_offsets_nuw_inbounds
547+
; CHECK: liveins: $x0
548+
; CHECK-NEXT: {{ $}}
549+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
550+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 11
551+
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
552+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s8))
553+
; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
554+
; CHECK-NEXT: RET_ReallyLR implicit $w0
555+
%0:_(p0) = COPY $x0
556+
%1:_(s64) = G_CONSTANT i64 10
557+
%2:_(s64) = G_CONSTANT i64 1
558+
%3:_(p0) = nuw nusw inbounds G_PTR_ADD %0, %1
559+
%4:_(p0) = nuw nusw inbounds G_PTR_ADD %3(p0), %2
560+
%7:_(s32) = G_LOAD %4(p0) :: (load 1)
561+
$w0 = COPY %7(s32)
562+
RET_ReallyLR implicit $w0
563+
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