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AMDGPU/GlobalISel: Look through copies for source modifiers
When all VOP instructions are legalized to VGPRs, any SGPR source modifiers will have a copy in the way.
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5 files changed

+10
-33
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5 files changed

+10
-33
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1990,12 +1990,12 @@ std::pair<Register, unsigned>
19901990
AMDGPUInstructionSelector::selectVOP3ModsImpl(
19911991
Register Src) const {
19921992
unsigned Mods = 0;
1993-
MachineInstr *MI = MRI->getVRegDef(Src);
1993+
MachineInstr *MI = getDefIgnoringCopies(Src, *MRI);
19941994

19951995
if (MI && MI->getOpcode() == AMDGPU::G_FNEG) {
19961996
Src = MI->getOperand(1).getReg();
19971997
Mods |= SISrcMods::NEG;
1998-
MI = MRI->getVRegDef(Src);
1998+
MI = getDefIgnoringCopies(Src, *MRI);
19991999
}
20002000

20012001
if (MI && MI->getOpcode() == AMDGPU::G_FABS) {

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir‎

Lines changed: 2 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -165,10 +165,7 @@ body: |
165165
; GFX6-LABEL: name: fadd_s32_fneg_copy_sgpr
166166
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
167167
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
168-
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
169-
; GFX6: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
170-
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_XOR_B32_]]
171-
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY2]], 0, 0, implicit $exec
168+
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec
172169
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
173170
%0:vgpr(s32) = COPY $vgpr0
174171
%1:sgpr(s32) = COPY $sgpr0
@@ -193,11 +190,7 @@ body: |
193190
; GFX6-LABEL: name: fadd_s32_copy_fneg_copy_fabs
194191
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
195192
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
196-
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
197-
; GFX6: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
198-
; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
199-
; GFX6: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[S_AND_B32_]], [[S_MOV_B32_1]], implicit-def $scc
200-
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[S_XOR_B32_]], 0, 0, implicit $exec
193+
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $exec
201194
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
202195
%0:vgpr(s32) = COPY $vgpr0
203196
%1:sgpr(s32) = COPY $sgpr0

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir‎

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -166,13 +166,7 @@ body: |
166166
; GFX6-LABEL: name: fadd_s64_fneg_copy_sgpr
167167
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
168168
; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
169-
; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
170-
; GFX6: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
171-
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
172-
; GFX6: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY3]], [[S_MOV_B32_]], implicit-def $scc
173-
; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
174-
; GFX6: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
175-
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY4]], 0, 0, implicit $exec
169+
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec
176170
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
177171
%0:vgpr(s64) = COPY $vgpr0_vgpr1
178172
%1:sgpr(s64) = COPY $sgpr0_sgpr1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir‎

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -206,26 +206,20 @@ body: |
206206
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
207207
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
208208
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
209-
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
210-
; GFX6: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec
211-
; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
209+
; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
212210
; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]
213211
; GFX9-DL-LABEL: name: fma_f32_copy_fneg_src2
214212
; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
215213
; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
216214
; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
217-
; GFX9-DL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
218-
; GFX9-DL: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec
219-
; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
215+
; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
220216
; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]]
221217
; GFX10-LABEL: name: fma_f32_copy_fneg_src2
222218
; GFX10: $vcc_hi = IMPLICIT_DEF
223219
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
224220
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
225221
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
226-
; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
227-
; GFX10: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec
228-
; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
222+
; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
229223
; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]]
230224
%0:vgpr(s32) = COPY $vgpr0
231225
%1:vgpr(s32) = COPY $vgpr1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir‎

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -175,18 +175,14 @@ body: |
175175
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
176176
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
177177
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
178-
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
179-
; GFX6: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec
180-
; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
178+
; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
181179
; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]
182180
; GFX10-LABEL: name: fmad_f32_copy_fneg_src2
183181
; GFX10: $vcc_hi = IMPLICIT_DEF
184182
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
185183
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
186184
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
187-
; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
188-
; GFX10: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec
189-
; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
185+
; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
190186
; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]
191187
%0:vgpr(s32) = COPY $vgpr0
192188
%1:vgpr(s32) = COPY $vgpr1

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