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[X86] SimplifyDemandedVectorElts - adjust X86ISD::ANDNP demanded elts based off constant masks
Similar to what we already do in combineAndnp, if either operand is a constant then we can improve the demanded elts/bits.
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6 files changed

+1421
-1446
lines changed

6 files changed

+1421
-1446
lines changed

‎llvm/lib/Target/X86/X86ISelLowering.cpp‎

Lines changed: 32 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -40540,21 +40540,43 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
4054040540
SDValue LHS = Op.getOperand(0);
4054140541
SDValue RHS = Op.getOperand(1);
4054240542

40543-
APInt RHSUndef, RHSZero;
40544-
if (SimplifyDemandedVectorElts(RHS, DemandedElts, RHSUndef, RHSZero, TLO,
40545-
Depth + 1))
40546-
return true;
40543+
auto GetDemandedMasks = [&](SDValue Op, bool Invert = false) {
40544+
APInt UndefElts;
40545+
SmallVector<APInt> EltBits;
40546+
int NumElts = VT.getVectorNumElements();
40547+
int EltSizeInBits = VT.getScalarSizeInBits();
40548+
APInt OpBits = APInt::getAllOnes(EltSizeInBits);
40549+
APInt OpElts = DemandedElts;
40550+
if (getTargetConstantBitsFromNode(Op, EltSizeInBits, UndefElts,
40551+
EltBits)) {
40552+
OpBits.clearAllBits();
40553+
OpElts.clearAllBits();
40554+
for (int I = 0; I != NumElts; ++I)
40555+
if (DemandedElts[I] && ((Invert && !EltBits[I].isAllOnes()) ||
40556+
(!Invert && !EltBits[I].isZero()))) {
40557+
OpBits |= Invert ? ~EltBits[I] : EltBits[I];
40558+
OpElts.setBit(I);
40559+
}
40560+
}
40561+
return std::make_pair(OpBits, OpElts);
40562+
};
40563+
std::pair<APInt, APInt> DemandLHS = GetDemandedMasks(RHS);
40564+
std::pair<APInt, APInt> DemandRHS = GetDemandedMasks(LHS, true);
4054740565

4054840566
APInt LHSUndef, LHSZero;
40549-
if (SimplifyDemandedVectorElts(LHS, DemandedElts, LHSUndef, LHSZero, TLO,
40550-
Depth + 1))
40567+
APInt RHSUndef, RHSZero;
40568+
if (SimplifyDemandedVectorElts(LHS, DemandLHS.second, LHSUndef, LHSZero,
40569+
TLO, Depth + 1))
40570+
return true;
40571+
if (SimplifyDemandedVectorElts(RHS, DemandRHS.second, RHSUndef, RHSZero,
40572+
TLO, Depth + 1))
4055140573
return true;
4055240574

4055340575
if (!DemandedElts.isAllOnes()) {
40554-
SDValue NewLHS = SimplifyMultipleUseDemandedVectorElts(
40555-
LHS, DemandedElts, TLO.DAG, Depth + 1);
40556-
SDValue NewRHS = SimplifyMultipleUseDemandedVectorElts(
40557-
RHS, DemandedElts, TLO.DAG, Depth + 1);
40576+
SDValue NewLHS = SimplifyMultipleUseDemandedBits(
40577+
LHS, DemandLHS.first, DemandLHS.second, TLO.DAG, Depth + 1);
40578+
SDValue NewRHS = SimplifyMultipleUseDemandedBits(
40579+
RHS, DemandRHS.first, DemandRHS.second, TLO.DAG, Depth + 1);
4055840580
if (NewLHS || NewRHS) {
4055940581
NewLHS = NewLHS ? NewLHS : LHS;
4056040582
NewRHS = NewRHS ? NewRHS : RHS;

‎llvm/test/CodeGen/X86/vector-fshl-512.ll‎

Lines changed: 12 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -544,17 +544,15 @@ define <16 x i32> @splatvar_funnnel_v16i32(<16 x i32> %x, <16 x i32> %y, <16 x i
544544
define <32 x i16> @splatvar_funnnel_v32i16(<32 x i16> %x, <32 x i16> %y, <32 x i16> %amt) nounwind {
545545
; AVX512F-LABEL: splatvar_funnnel_v32i16:
546546
; AVX512F: # %bb.0:
547-
; AVX512F-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15]
548-
; AVX512F-NEXT: vpand %xmm3, %xmm2, %xmm2
549-
; AVX512F-NEXT: vpmovzxwq {{.*#+}} xmm4 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
550-
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm5
551-
; AVX512F-NEXT: vpsllw %xmm4, %ymm5, %ymm5
547+
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3
548+
; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm4
549+
; AVX512F-NEXT: vpsllw %xmm4, %ymm3, %ymm3
552550
; AVX512F-NEXT: vpsllw %xmm4, %ymm0, %ymm0
553-
; AVX512F-NEXT: vinserti64x4 $1, %ymm5, %zmm0, %zmm0
554-
; AVX512F-NEXT: vpandn %xmm3, %xmm2, %xmm2
555-
; AVX512F-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
551+
; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0
556552
; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm3
557553
; AVX512F-NEXT: vpsrlw $1, %ymm3, %ymm3
554+
; AVX512F-NEXT: vpandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
555+
; AVX512F-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
558556
; AVX512F-NEXT: vpsrlw %xmm2, %ymm3, %ymm3
559557
; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
560558
; AVX512F-NEXT: vpsrlw %xmm2, %ymm1, %ymm1
@@ -564,17 +562,15 @@ define <32 x i16> @splatvar_funnnel_v32i16(<32 x i16> %x, <32 x i16> %y, <32 x i
564562
;
565563
; AVX512VL-LABEL: splatvar_funnnel_v32i16:
566564
; AVX512VL: # %bb.0:
567-
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15]
568-
; AVX512VL-NEXT: vpand %xmm3, %xmm2, %xmm2
569-
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm4 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
570-
; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm5
571-
; AVX512VL-NEXT: vpsllw %xmm4, %ymm5, %ymm5
565+
; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm3
566+
; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm4
567+
; AVX512VL-NEXT: vpsllw %xmm4, %ymm3, %ymm3
572568
; AVX512VL-NEXT: vpsllw %xmm4, %ymm0, %ymm0
573-
; AVX512VL-NEXT: vinserti64x4 $1, %ymm5, %zmm0, %zmm0
574-
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm2
575-
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
569+
; AVX512VL-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0
576570
; AVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm3
577571
; AVX512VL-NEXT: vpsrlw $1, %ymm3, %ymm3
572+
; AVX512VL-NEXT: vpandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
573+
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
578574
; AVX512VL-NEXT: vpsrlw %xmm2, %ymm3, %ymm3
579575
; AVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm1
580576
; AVX512VL-NEXT: vpsrlw %xmm2, %ymm1, %ymm1

‎llvm/test/CodeGen/X86/vector-fshr-512.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -547,8 +547,8 @@ define <32 x i16> @splatvar_funnnel_v32i16(<32 x i16> %x, <32 x i16> %y, <32 x i
547547
; AVX512F-LABEL: splatvar_funnnel_v32i16:
548548
; AVX512F: # %bb.0:
549549
; AVX512F-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15]
550-
; AVX512F-NEXT: vpand %xmm3, %xmm2, %xmm2
551-
; AVX512F-NEXT: vpmovzxwq {{.*#+}} xmm4 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
550+
; AVX512F-NEXT: vpand %xmm3, %xmm2, %xmm4
551+
; AVX512F-NEXT: vpmovzxwq {{.*#+}} xmm4 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero
552552
; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm5
553553
; AVX512F-NEXT: vpsrlw %xmm4, %ymm5, %ymm5
554554
; AVX512F-NEXT: vpsrlw %xmm4, %ymm1, %ymm1
@@ -567,8 +567,8 @@ define <32 x i16> @splatvar_funnnel_v32i16(<32 x i16> %x, <32 x i16> %y, <32 x i
567567
; AVX512VL-LABEL: splatvar_funnnel_v32i16:
568568
; AVX512VL: # %bb.0:
569569
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15]
570-
; AVX512VL-NEXT: vpand %xmm3, %xmm2, %xmm2
571-
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm4 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
570+
; AVX512VL-NEXT: vpand %xmm3, %xmm2, %xmm4
571+
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm4 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero
572572
; AVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm5
573573
; AVX512VL-NEXT: vpsrlw %xmm4, %ymm5, %ymm5
574574
; AVX512VL-NEXT: vpsrlw %xmm4, %ymm1, %ymm1

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