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[RISCV] Add Zfh RUN lines to calling-conv-half.ll. NFC (#156562)
We had these RUN lines in our downstream and I couldn't tell for sure that we had another Zfh calling convention test upstream. Note we should fix the stack test to also exhaust the GPRs to make it test the stack for ilp32f/lp64f. This was an existing issue in the testing when F was enabled.
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‎llvm/test/CodeGen/RISCV/calling-conv-half.ll‎

Lines changed: 253 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,10 +7,18 @@
77
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64-LP64F
88
; RUN: llc -mtriple=riscv32 -mattr=+f,+zfhmin -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32ZFHMIN
99
; RUN: llc -mtriple=riscv64 -mattr=+f,+zfhmin -target-abi=lp64f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64-LP64ZFHMIN
10+
; RUN: llc -mtriple=riscv32 -mattr=+f -mattr=+zfh -verify-machineinstrs -target-abi ilp32 -O1 < %s \
11+
; RUN: | FileCheck %s -check-prefix=RV32-ZFH-ILP32
12+
; RUN: llc -mtriple=riscv32 -mattr=+f -mattr=+zfh -verify-machineinstrs -target-abi ilp32f -O1 < %s \
13+
; RUN: | FileCheck %s -check-prefix=RV32-ZFH-ILP32F
14+
; RUN: llc -mtriple=riscv64 -mattr=+f -mattr=+zfh -verify-machineinstrs -target-abi lp64 -O1 < %s \
15+
; RUN: | FileCheck %s -check-prefix=RV64-ZFH-LP64
16+
; RUN: llc -mtriple=riscv64 -mattr=+f -mattr=+zfh -verify-machineinstrs -target-abi lp64f -O1 < %s \
17+
; RUN: | FileCheck %s -check-prefix=RV64-ZFH-LP64F
1018

11-
; Tests passing half arguments and returns without Zfh.
12-
; Covers with and without F extension and ilp32f/ilp64f
13-
; calling conventions.
19+
; Tests passing half arguments and returns.
20+
; Covers with and without F extension, with and without Zfhmin/Zfh extensions,
21+
; and ilp32f/ilp64f calling conventions.
1422

1523
define i32 @callee_half_in_regs(i32 %a, half %b) nounwind {
1624
; RV32I-LABEL: callee_half_in_regs:
@@ -118,6 +126,32 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind {
118126
; RV64-LP64ZFHMIN-NEXT: fcvt.w.s a1, fa5, rtz
119127
; RV64-LP64ZFHMIN-NEXT: addw a0, a0, a1
120128
; RV64-LP64ZFHMIN-NEXT: ret
129+
;
130+
; RV32-ZFH-ILP32-LABEL: callee_half_in_regs:
131+
; RV32-ZFH-ILP32: # %bb.0:
132+
; RV32-ZFH-ILP32-NEXT: fmv.h.x fa5, a1
133+
; RV32-ZFH-ILP32-NEXT: fcvt.w.h a1, fa5, rtz
134+
; RV32-ZFH-ILP32-NEXT: add a0, a0, a1
135+
; RV32-ZFH-ILP32-NEXT: ret
136+
;
137+
; RV32-ZFH-ILP32F-LABEL: callee_half_in_regs:
138+
; RV32-ZFH-ILP32F: # %bb.0:
139+
; RV32-ZFH-ILP32F-NEXT: fcvt.w.h a1, fa0, rtz
140+
; RV32-ZFH-ILP32F-NEXT: add a0, a0, a1
141+
; RV32-ZFH-ILP32F-NEXT: ret
142+
;
143+
; RV64-ZFH-LP64-LABEL: callee_half_in_regs:
144+
; RV64-ZFH-LP64: # %bb.0:
145+
; RV64-ZFH-LP64-NEXT: fmv.h.x fa5, a1
146+
; RV64-ZFH-LP64-NEXT: fcvt.w.h a1, fa5, rtz
147+
; RV64-ZFH-LP64-NEXT: addw a0, a0, a1
148+
; RV64-ZFH-LP64-NEXT: ret
149+
;
150+
; RV64-ZFH-LP64F-LABEL: callee_half_in_regs:
151+
; RV64-ZFH-LP64F: # %bb.0:
152+
; RV64-ZFH-LP64F-NEXT: fcvt.w.h a1, fa0, rtz
153+
; RV64-ZFH-LP64F-NEXT: addw a0, a0, a1
154+
; RV64-ZFH-LP64F-NEXT: ret
121155
%b_fptosi = fptosi half %b to i32
122156
%1 = add i32 %a, %b_fptosi
123157
ret i32 %1
@@ -215,6 +249,52 @@ define i32 @caller_half_in_regs() nounwind {
215249
; RV64-LP64ZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
216250
; RV64-LP64ZFHMIN-NEXT: addi sp, sp, 16
217251
; RV64-LP64ZFHMIN-NEXT: ret
252+
;
253+
; RV32-ZFH-ILP32-LABEL: caller_half_in_regs:
254+
; RV32-ZFH-ILP32: # %bb.0:
255+
; RV32-ZFH-ILP32-NEXT: addi sp, sp, -16
256+
; RV32-ZFH-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
257+
; RV32-ZFH-ILP32-NEXT: li a0, 1
258+
; RV32-ZFH-ILP32-NEXT: lui a1, 4
259+
; RV32-ZFH-ILP32-NEXT: call callee_half_in_regs
260+
; RV32-ZFH-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
261+
; RV32-ZFH-ILP32-NEXT: addi sp, sp, 16
262+
; RV32-ZFH-ILP32-NEXT: ret
263+
;
264+
; RV32-ZFH-ILP32F-LABEL: caller_half_in_regs:
265+
; RV32-ZFH-ILP32F: # %bb.0:
266+
; RV32-ZFH-ILP32F-NEXT: addi sp, sp, -16
267+
; RV32-ZFH-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
268+
; RV32-ZFH-ILP32F-NEXT: lui a0, 4
269+
; RV32-ZFH-ILP32F-NEXT: fmv.h.x fa0, a0
270+
; RV32-ZFH-ILP32F-NEXT: li a0, 1
271+
; RV32-ZFH-ILP32F-NEXT: call callee_half_in_regs
272+
; RV32-ZFH-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
273+
; RV32-ZFH-ILP32F-NEXT: addi sp, sp, 16
274+
; RV32-ZFH-ILP32F-NEXT: ret
275+
;
276+
; RV64-ZFH-LP64-LABEL: caller_half_in_regs:
277+
; RV64-ZFH-LP64: # %bb.0:
278+
; RV64-ZFH-LP64-NEXT: addi sp, sp, -16
279+
; RV64-ZFH-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
280+
; RV64-ZFH-LP64-NEXT: li a0, 1
281+
; RV64-ZFH-LP64-NEXT: lui a1, 4
282+
; RV64-ZFH-LP64-NEXT: call callee_half_in_regs
283+
; RV64-ZFH-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
284+
; RV64-ZFH-LP64-NEXT: addi sp, sp, 16
285+
; RV64-ZFH-LP64-NEXT: ret
286+
;
287+
; RV64-ZFH-LP64F-LABEL: caller_half_in_regs:
288+
; RV64-ZFH-LP64F: # %bb.0:
289+
; RV64-ZFH-LP64F-NEXT: addi sp, sp, -16
290+
; RV64-ZFH-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
291+
; RV64-ZFH-LP64F-NEXT: lui a0, 4
292+
; RV64-ZFH-LP64F-NEXT: fmv.h.x fa0, a0
293+
; RV64-ZFH-LP64F-NEXT: li a0, 1
294+
; RV64-ZFH-LP64F-NEXT: call callee_half_in_regs
295+
; RV64-ZFH-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
296+
; RV64-ZFH-LP64F-NEXT: addi sp, sp, 16
297+
; RV64-ZFH-LP64F-NEXT: ret
218298
%1 = call i32 @callee_half_in_regs(i32 1, half 2.0)
219299
ret i32 %1
220300
}
@@ -323,6 +403,32 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
323403
; RV64-LP64ZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
324404
; RV64-LP64ZFHMIN-NEXT: addw a0, a7, a0
325405
; RV64-LP64ZFHMIN-NEXT: ret
406+
;
407+
; RV32-ZFH-ILP32-LABEL: callee_half_on_stack:
408+
; RV32-ZFH-ILP32: # %bb.0:
409+
; RV32-ZFH-ILP32-NEXT: flh fa5, 0(sp)
410+
; RV32-ZFH-ILP32-NEXT: fcvt.w.h a0, fa5, rtz
411+
; RV32-ZFH-ILP32-NEXT: add a0, a7, a0
412+
; RV32-ZFH-ILP32-NEXT: ret
413+
;
414+
; RV32-ZFH-ILP32F-LABEL: callee_half_on_stack:
415+
; RV32-ZFH-ILP32F: # %bb.0:
416+
; RV32-ZFH-ILP32F-NEXT: fcvt.w.h a0, fa0, rtz
417+
; RV32-ZFH-ILP32F-NEXT: add a0, a7, a0
418+
; RV32-ZFH-ILP32F-NEXT: ret
419+
;
420+
; RV64-ZFH-LP64-LABEL: callee_half_on_stack:
421+
; RV64-ZFH-LP64: # %bb.0:
422+
; RV64-ZFH-LP64-NEXT: flh fa5, 0(sp)
423+
; RV64-ZFH-LP64-NEXT: fcvt.w.h a0, fa5, rtz
424+
; RV64-ZFH-LP64-NEXT: addw a0, a7, a0
425+
; RV64-ZFH-LP64-NEXT: ret
426+
;
427+
; RV64-ZFH-LP64F-LABEL: callee_half_on_stack:
428+
; RV64-ZFH-LP64F: # %bb.0:
429+
; RV64-ZFH-LP64F-NEXT: fcvt.w.h a0, fa0, rtz
430+
; RV64-ZFH-LP64F-NEXT: addw a0, a7, a0
431+
; RV64-ZFH-LP64F-NEXT: ret
326432
%1 = fptosi half %i to i32
327433
%2 = add i32 %h, %1
328434
ret i32 %2
@@ -484,6 +590,84 @@ define i32 @caller_half_on_stack() nounwind {
484590
; RV64-LP64ZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
485591
; RV64-LP64ZFHMIN-NEXT: addi sp, sp, 16
486592
; RV64-LP64ZFHMIN-NEXT: ret
593+
;
594+
; RV32-ZFH-ILP32-LABEL: caller_half_on_stack:
595+
; RV32-ZFH-ILP32: # %bb.0:
596+
; RV32-ZFH-ILP32-NEXT: addi sp, sp, -16
597+
; RV32-ZFH-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
598+
; RV32-ZFH-ILP32-NEXT: lui a4, %hi(.LCPI3_0)
599+
; RV32-ZFH-ILP32-NEXT: li a0, 1
600+
; RV32-ZFH-ILP32-NEXT: li a1, 2
601+
; RV32-ZFH-ILP32-NEXT: li a2, 3
602+
; RV32-ZFH-ILP32-NEXT: li a3, 4
603+
; RV32-ZFH-ILP32-NEXT: flh fa5, %lo(.LCPI3_0)(a4)
604+
; RV32-ZFH-ILP32-NEXT: li a4, 5
605+
; RV32-ZFH-ILP32-NEXT: li a5, 6
606+
; RV32-ZFH-ILP32-NEXT: li a6, 7
607+
; RV32-ZFH-ILP32-NEXT: li a7, 8
608+
; RV32-ZFH-ILP32-NEXT: fsh fa5, 0(sp)
609+
; RV32-ZFH-ILP32-NEXT: call callee_half_on_stack
610+
; RV32-ZFH-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
611+
; RV32-ZFH-ILP32-NEXT: addi sp, sp, 16
612+
; RV32-ZFH-ILP32-NEXT: ret
613+
;
614+
; RV32-ZFH-ILP32F-LABEL: caller_half_on_stack:
615+
; RV32-ZFH-ILP32F: # %bb.0:
616+
; RV32-ZFH-ILP32F-NEXT: addi sp, sp, -16
617+
; RV32-ZFH-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
618+
; RV32-ZFH-ILP32F-NEXT: lui a4, %hi(.LCPI3_0)
619+
; RV32-ZFH-ILP32F-NEXT: li a0, 1
620+
; RV32-ZFH-ILP32F-NEXT: li a1, 2
621+
; RV32-ZFH-ILP32F-NEXT: li a2, 3
622+
; RV32-ZFH-ILP32F-NEXT: li a3, 4
623+
; RV32-ZFH-ILP32F-NEXT: flh fa0, %lo(.LCPI3_0)(a4)
624+
; RV32-ZFH-ILP32F-NEXT: li a4, 5
625+
; RV32-ZFH-ILP32F-NEXT: li a5, 6
626+
; RV32-ZFH-ILP32F-NEXT: li a6, 7
627+
; RV32-ZFH-ILP32F-NEXT: li a7, 8
628+
; RV32-ZFH-ILP32F-NEXT: call callee_half_on_stack
629+
; RV32-ZFH-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
630+
; RV32-ZFH-ILP32F-NEXT: addi sp, sp, 16
631+
; RV32-ZFH-ILP32F-NEXT: ret
632+
;
633+
; RV64-ZFH-LP64-LABEL: caller_half_on_stack:
634+
; RV64-ZFH-LP64: # %bb.0:
635+
; RV64-ZFH-LP64-NEXT: addi sp, sp, -16
636+
; RV64-ZFH-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
637+
; RV64-ZFH-LP64-NEXT: lui a4, %hi(.LCPI3_0)
638+
; RV64-ZFH-LP64-NEXT: li a0, 1
639+
; RV64-ZFH-LP64-NEXT: li a1, 2
640+
; RV64-ZFH-LP64-NEXT: li a2, 3
641+
; RV64-ZFH-LP64-NEXT: li a3, 4
642+
; RV64-ZFH-LP64-NEXT: flh fa5, %lo(.LCPI3_0)(a4)
643+
; RV64-ZFH-LP64-NEXT: li a4, 5
644+
; RV64-ZFH-LP64-NEXT: li a5, 6
645+
; RV64-ZFH-LP64-NEXT: li a6, 7
646+
; RV64-ZFH-LP64-NEXT: li a7, 8
647+
; RV64-ZFH-LP64-NEXT: fsh fa5, 0(sp)
648+
; RV64-ZFH-LP64-NEXT: call callee_half_on_stack
649+
; RV64-ZFH-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
650+
; RV64-ZFH-LP64-NEXT: addi sp, sp, 16
651+
; RV64-ZFH-LP64-NEXT: ret
652+
;
653+
; RV64-ZFH-LP64F-LABEL: caller_half_on_stack:
654+
; RV64-ZFH-LP64F: # %bb.0:
655+
; RV64-ZFH-LP64F-NEXT: addi sp, sp, -16
656+
; RV64-ZFH-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
657+
; RV64-ZFH-LP64F-NEXT: lui a4, %hi(.LCPI3_0)
658+
; RV64-ZFH-LP64F-NEXT: li a0, 1
659+
; RV64-ZFH-LP64F-NEXT: li a1, 2
660+
; RV64-ZFH-LP64F-NEXT: li a2, 3
661+
; RV64-ZFH-LP64F-NEXT: li a3, 4
662+
; RV64-ZFH-LP64F-NEXT: flh fa0, %lo(.LCPI3_0)(a4)
663+
; RV64-ZFH-LP64F-NEXT: li a4, 5
664+
; RV64-ZFH-LP64F-NEXT: li a5, 6
665+
; RV64-ZFH-LP64F-NEXT: li a6, 7
666+
; RV64-ZFH-LP64F-NEXT: li a7, 8
667+
; RV64-ZFH-LP64F-NEXT: call callee_half_on_stack
668+
; RV64-ZFH-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
669+
; RV64-ZFH-LP64F-NEXT: addi sp, sp, 16
670+
; RV64-ZFH-LP64F-NEXT: ret
487671
%1 = call i32 @callee_half_on_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, half 10.0)
488672
ret i32 %1
489673
}
@@ -536,6 +720,30 @@ define half @callee_half_ret() nounwind {
536720
; RV64-LP64ZFHMIN-NEXT: lui a0, %hi(.LCPI4_0)
537721
; RV64-LP64ZFHMIN-NEXT: flh fa0, %lo(.LCPI4_0)(a0)
538722
; RV64-LP64ZFHMIN-NEXT: ret
723+
;
724+
; RV32-ZFH-ILP32-LABEL: callee_half_ret:
725+
; RV32-ZFH-ILP32: # %bb.0:
726+
; RV32-ZFH-ILP32-NEXT: li a0, 15
727+
; RV32-ZFH-ILP32-NEXT: slli a0, a0, 10
728+
; RV32-ZFH-ILP32-NEXT: ret
729+
;
730+
; RV32-ZFH-ILP32F-LABEL: callee_half_ret:
731+
; RV32-ZFH-ILP32F: # %bb.0:
732+
; RV32-ZFH-ILP32F-NEXT: lui a0, %hi(.LCPI4_0)
733+
; RV32-ZFH-ILP32F-NEXT: flh fa0, %lo(.LCPI4_0)(a0)
734+
; RV32-ZFH-ILP32F-NEXT: ret
735+
;
736+
; RV64-ZFH-LP64-LABEL: callee_half_ret:
737+
; RV64-ZFH-LP64: # %bb.0:
738+
; RV64-ZFH-LP64-NEXT: li a0, 15
739+
; RV64-ZFH-LP64-NEXT: slli a0, a0, 10
740+
; RV64-ZFH-LP64-NEXT: ret
741+
;
742+
; RV64-ZFH-LP64F-LABEL: callee_half_ret:
743+
; RV64-ZFH-LP64F: # %bb.0:
744+
; RV64-ZFH-LP64F-NEXT: lui a0, %hi(.LCPI4_0)
745+
; RV64-ZFH-LP64F-NEXT: flh fa0, %lo(.LCPI4_0)(a0)
746+
; RV64-ZFH-LP64F-NEXT: ret
539747
ret half 1.0
540748
}
541749

@@ -633,6 +841,48 @@ define i32 @caller_half_ret() nounwind {
633841
; RV64-LP64ZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
634842
; RV64-LP64ZFHMIN-NEXT: addi sp, sp, 16
635843
; RV64-LP64ZFHMIN-NEXT: ret
844+
;
845+
; RV32-ZFH-ILP32-LABEL: caller_half_ret:
846+
; RV32-ZFH-ILP32: # %bb.0:
847+
; RV32-ZFH-ILP32-NEXT: addi sp, sp, -16
848+
; RV32-ZFH-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
849+
; RV32-ZFH-ILP32-NEXT: call callee_half_ret
850+
; RV32-ZFH-ILP32-NEXT: fmv.h.x fa5, a0
851+
; RV32-ZFH-ILP32-NEXT: fcvt.w.h a0, fa5, rtz
852+
; RV32-ZFH-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
853+
; RV32-ZFH-ILP32-NEXT: addi sp, sp, 16
854+
; RV32-ZFH-ILP32-NEXT: ret
855+
;
856+
; RV32-ZFH-ILP32F-LABEL: caller_half_ret:
857+
; RV32-ZFH-ILP32F: # %bb.0:
858+
; RV32-ZFH-ILP32F-NEXT: addi sp, sp, -16
859+
; RV32-ZFH-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
860+
; RV32-ZFH-ILP32F-NEXT: call callee_half_ret
861+
; RV32-ZFH-ILP32F-NEXT: fcvt.w.h a0, fa0, rtz
862+
; RV32-ZFH-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
863+
; RV32-ZFH-ILP32F-NEXT: addi sp, sp, 16
864+
; RV32-ZFH-ILP32F-NEXT: ret
865+
;
866+
; RV64-ZFH-LP64-LABEL: caller_half_ret:
867+
; RV64-ZFH-LP64: # %bb.0:
868+
; RV64-ZFH-LP64-NEXT: addi sp, sp, -16
869+
; RV64-ZFH-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
870+
; RV64-ZFH-LP64-NEXT: call callee_half_ret
871+
; RV64-ZFH-LP64-NEXT: fmv.h.x fa5, a0
872+
; RV64-ZFH-LP64-NEXT: fcvt.w.h a0, fa5, rtz
873+
; RV64-ZFH-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
874+
; RV64-ZFH-LP64-NEXT: addi sp, sp, 16
875+
; RV64-ZFH-LP64-NEXT: ret
876+
;
877+
; RV64-ZFH-LP64F-LABEL: caller_half_ret:
878+
; RV64-ZFH-LP64F: # %bb.0:
879+
; RV64-ZFH-LP64F-NEXT: addi sp, sp, -16
880+
; RV64-ZFH-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
881+
; RV64-ZFH-LP64F-NEXT: call callee_half_ret
882+
; RV64-ZFH-LP64F-NEXT: fcvt.w.h a0, fa0, rtz
883+
; RV64-ZFH-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
884+
; RV64-ZFH-LP64F-NEXT: addi sp, sp, 16
885+
; RV64-ZFH-LP64F-NEXT: ret
636886
%1 = call half @callee_half_ret()
637887
%2 = fptosi half %1 to i32
638888
ret i32 %2

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