Update code comments (addressing review comments)

hazzlim · hazzlim · commit 8daee4030a40 · 2024-05-10T08:59:39.000Z
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1852,7 +1852,6 @@ bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT,
 }
 
 bool AArch64TargetLowering::shouldExpandCttzElements(EVT VT) const {
-  // Only SVE and SME architectures support BRKB and CNTP instructions.
   if (!Subtarget->hasSVEorSME())
     return true;
 
diff --git a/llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll b/llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
@@ -137,7 +137,7 @@ define i64 @vscale_4096_poison(<vscale x 16 x i8> %a) #1 {
   ret i64 %res
 }
 
-; MATCH WITH BRKB + CNTP
+; EFFICIENT LOWERING USING BRKB
 
 define i32 @ctz_nxv2i1(<vscale x 2 x i1> %a) {
 ; CHECK-LABEL: ctz_nxv2i1:

Original file line number	Diff line number	Diff line change
`@@ -1852,7 +1852,6 @@ bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT,`
`1852`	`1852`	`}`
`1853`	`1853`
`1854`	`1854`	`bool AArch64TargetLowering::shouldExpandCttzElements(EVT VT) const {`
`1855`		`- // Only SVE and SME architectures support BRKB and CNTP instructions.`
`1856`	`1855`	`if (!Subtarget->hasSVEorSME())`
`1857`	`1856`	`return true;`
`1858`	`1857`
Original file line number	Diff line number	Diff line change
`@@ -137,7 +137,7 @@ define i64 @vscale_4096_poison(<vscale x 16 x i8> %a) #1 {`
`137`	`137`	`ret i64 %res`
`138`	`138`	`}`
`139`	`139`
`140`		`-; MATCH WITH BRKB + CNTP`
	`140`	`+; EFFICIENT LOWERING USING BRKB`
`141`	`141`
`142`	`142`	`define i32 @ctz_nxv2i1(<vscale x 2 x i1> %a) {`
`143`	`143`	`; CHECK-LABEL: ctz_nxv2i1:`