AMDGPU: Replace insertelement poison with insertelement undef

This is the bulk update with perl, with cases which require additional
update left for later.

Author: arsenm

llvm/test/CodeGen/AMDGPU/add3.ll

@@ -181,7 +181,7 @@ define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x
   %inner = add i32 %a, %b
   %outer = add i32 %inner, %c
   %x1 = mul i32 %outer, %x
-  %r1 = insertelement <2 x i32> undef, i32 %outer, i32 0
+  %r1 = insertelement <2 x i32> poison, i32 %outer, i32 0
   %r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1
   %bc = bitcast <2 x i32> %r0 to <2 x float>
   ret <2 x float> %bc
@@ -207,7 +207,7 @@ define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
 ; GFX10-NEXT:    ; return to shader part epilog
   %inner = add i32 %a, %b
   %outer = add i32 %inner, %c
-  %r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
+  %r1 = insertelement <2 x i32> poison, i32 %inner, i32 0
   %r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1
   %bc = bitcast <2 x i32> %r0 to <2 x float>
   ret <2 x float> %bc

llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll

@@ -17,7 +17,7 @@ define amdgpu_hs void @_amdgpu_hs_main(i32 inreg %arg, i32 inreg %arg1, i32 inre
 
 .beginls:                                         ; preds = %.entry
   %tmp15 = extractelement <6 x i32> %arg8, i32 3
-  %.0.vec.insert.i = insertelement <2 x i32> undef, i32 %tmp15, i32 0
+  %.0.vec.insert.i = insertelement <2 x i32> poison, i32 %tmp15, i32 0
   %.4.vec.insert.i = shufflevector <2 x i32> %.0.vec.insert.i, <2 x i32> undef, <2 x i32> <i32 0, i32 3>
   %tmp16 = bitcast <2 x i32> %.4.vec.insert.i to i64
   br label %.endls

llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll

@@ -36,7 +36,7 @@ bb:
   %tmp21 = getelementptr inbounds <8 x i8>, ptr addrspace(1) %arg, i64 4
   %tmp23 = load <16 x i8>, ptr addrspace(1) %tmp21, align 16
   %tmp24 = extractelement <16 x i8> %tmp23, i64 3
-  %tmp1 = insertelement <16 x i8> undef, i8 %tmp3, i32 2
+  %tmp1 = insertelement <16 x i8> poison, i8 %tmp3, i32 2
   %tmp4 = insertelement <16 x i8> %tmp1, i8 0, i32 3
   %tmp5 = insertelement <16 x i8> %tmp4, i8 0, i32 4
   %tmp7 = insertelement <16 x i8> %tmp5, i8 %tmp6, i32 5

llvm/test/CodeGen/AMDGPU/anyext.ll

@@ -187,7 +187,7 @@ define amdgpu_kernel void @anyext_v2i16_to_v2i32() #0 {
 ; GFX9-NEXT:    s_endpgm
 bb:
   %tmp = load i16, ptr addrspace(1) undef, align 2
-  %tmp2 = insertelement <2 x i16> undef, i16 %tmp, i32 1
+  %tmp2 = insertelement <2 x i16> poison, i16 %tmp, i32 1
   %tmp4 = and <2 x i16> %tmp2, <i16 -32767, i16 -32767>
   %tmp5 = zext <2 x i16> %tmp4 to <2 x i32>
   %tmp6 = shl nuw <2 x i32> %tmp5, <i32 16, i32 16>

llvm/test/CodeGen/AMDGPU/bf16-conversions.ll

@@ -189,7 +189,7 @@ define amdgpu_ps float @fptrunc_f32_f32_to_v2bf16(float %a, float %b) {
 entry:
   %a.cvt = fptrunc float %a to bfloat
   %b.cvt = fptrunc float %b to bfloat
-  %v2.1 = insertelement <2 x bfloat> undef, bfloat %a.cvt, i32 0
+  %v2.1 = insertelement <2 x bfloat> poison, bfloat %a.cvt, i32 0
   %v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
   %ret = bitcast <2 x bfloat> %v2.2 to float
   ret float %ret
@@ -226,7 +226,7 @@ entry:
   %a.cvt = fptrunc float %a.neg to bfloat
   %b.abs = call float @llvm.fabs.f32(float %b)
   %b.cvt = fptrunc float %b.abs to bfloat
-  %v2.1 = insertelement <2 x bfloat> undef, bfloat %a.cvt, i32 0
+  %v2.1 = insertelement <2 x bfloat> poison, bfloat %a.cvt, i32 0
   %v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
   %ret = bitcast <2 x bfloat> %v2.2 to float
   ret float %ret

llvm/test/CodeGen/AMDGPU/bfi_nested.ll

@@ -297,7 +297,7 @@ define amdgpu_kernel void @v_bfi_dont_applied_for_scalar_ops(ptr addrspace(1) %o
 ; GCN-NEXT:    s_endpgm
   %shift = lshr i32 %b, 16
   %tr = trunc i32 %shift to i16
-  %tmp = insertelement <2 x i16> undef, i16 %a, i32 0
+  %tmp = insertelement <2 x i16> poison, i16 %a, i32 0
   %vec = insertelement <2 x i16> %tmp, i16 %tr, i32 1
   %val = bitcast <2 x i16> %vec to i32
   store i32 %val, ptr addrspace(1) %out, align 4

llvm/test/CodeGen/AMDGPU/big_alu.ll

@@ -48,9 +48,9 @@ bb1789:                                           ; preds = %bb1750
   %i1883 = shufflevector <3 x i32> %i1882, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
   %i1884 = bitcast <4 x i32> %i1883 to <4 x float>
   %i1885 = shufflevector <4 x float> %i1884, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
-  %i1886 = insertelement <3 x i32> undef, i32 %i1819, i64 0
+  %i1886 = insertelement <3 x i32> poison, i32 %i1819, i64 0
   %i1887 = bitcast <3 x i32> %i1886 to <3 x float>
-  %i1888 = insertelement <3 x i32> undef, i32 %i1801, i64 0
+  %i1888 = insertelement <3 x i32> poison, i32 %i1801, i64 0
   %i1889 = bitcast <3 x i32> %i1888 to <3 x float>
   %i1890 = fmul reassoc nnan nsz arcp contract afn <3 x float> %i1887, %i1889
   %i1891 = shufflevector <3 x float> %i1890, <3 x float> poison, <3 x i32> zeroinitializer

llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll

@@ -15,15 +15,15 @@ entry:
   %tmp2 = getelementptr inbounds double, ptr addrspace(1) %tmp1, i64 undef
   %tmp4 = load <3 x double>, ptr addrspace(1) %tmp2, align 8, !tbaa !6
   %tmp5 = extractelement <3 x double> %tmp4, i32 1
-  %tmp6 = insertelement <3 x double> undef, double %tmp5, i32 1
-  %tmp7 = insertelement <3 x double> %tmp6, double undef, i32 2
+  %tmp6 = insertelement <3 x double> poison, double %tmp5, i32 1
+  %tmp7 = insertelement <3 x double> %tmp6, double poison, i32 2
   %tmp8 = load <3 x double>, ptr addrspace(1) undef, align 8, !tbaa !6
   %tmp9 = extractelement <3 x double> %tmp8, i32 2
-  %tmp10 = insertelement <3 x double> undef, double %tmp9, i32 2
+  %tmp10 = insertelement <3 x double> poison, double %tmp9, i32 2
   %tmp11 = fcmp olt <3 x double> %tmp10, %tmp7
   %tmp12 = select <3 x i1> %tmp11, <3 x double> zeroinitializer, <3 x double> <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>
   %tmp13 = extractelement <3 x double> %tmp12, i64 1
-  %tmp14 = insertelement <2 x double> undef, double %tmp13, i32 1
+  %tmp14 = insertelement <2 x double> poison, double %tmp13, i32 1
   store <2 x double> %tmp14, ptr addrspace(1) undef, align 8, !tbaa !6
   ret void
 }
@@ -42,12 +42,12 @@ entry:
   %tmp2 = getelementptr inbounds double, ptr addrspace(1) %tmp1, i64 undef
   %tmp4 = load <3 x double>, ptr addrspace(1) %tmp2, align 8, !tbaa !6
   %tmp5 = extractelement <3 x double> %tmp4, i32 1
-  %tmp6 = insertelement <3 x double> undef, double %tmp5, i32 1
-  %tmp7 = insertelement <3 x double> %tmp6, double undef, i32 2
+  %tmp6 = insertelement <3 x double> poison, double %tmp5, i32 1
+  %tmp7 = insertelement <3 x double> %tmp6, double poison, i32 2
   %tmp8 = load <3 x double>, ptr addrspace(1) undef, align 8, !tbaa !6
   %tmp9 = extractelement <3 x double> %tmp8, i32 1
-  %tmp10 = insertelement <3 x double> undef, double %tmp9, i32 1
-  %tmp11 = insertelement <3 x double> %tmp10, double undef, i32 2
+  %tmp10 = insertelement <3 x double> poison, double %tmp9, i32 1
+  %tmp11 = insertelement <3 x double> %tmp10, double poison, i32 2
   %tmp12 = fcmp olt <3 x double> %tmp11, %tmp7
   %tmp13 = select <3 x i1> %tmp12, <3 x double> zeroinitializer, <3 x double> <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>
   %tmp14 = extractelement <3 x double> %tmp13, i64 2

llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll

@@ -15,7 +15,7 @@ bb1:
   %tmp2 = phi half [ 0xH0000, %bb ], [ %tmp8, %bb1 ]
   %tmp3 = load volatile half, ptr null, align 536870912
   %tmp4 = bitcast half %tmp3 to i16
-  %tmp5 = insertelement <2 x i16> <i16 0, i16 undef>, i16 %tmp4, i32 1
+  %tmp5 = insertelement <2 x i16> <i16 0, i16 poison>, i16 %tmp4, i32 1
   store volatile half %tmp2, ptr %arg, align 2
   %tmp7 = bitcast <2 x i16> %tmp to <2 x half>
   %tmp8 = extractelement <2 x half> %tmp7, i32 0