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Commit 84fe120

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isBaseWithConstantOffset(Addr) -> Addr->isAnyAdd()
Op->isAnyAdd() -> Op.getOpcode() != ISD::SUB
1 parent 41b0c71 commit 84fe120

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2 files changed

+3
-3
lines changed

2 files changed

+3
-3
lines changed

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2982,8 +2982,8 @@ bool TargetLowering::SimplifyDemandedBits(
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Known = KnownBits::mul(KnownOp0, KnownOp1);
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} else { // Op.getOpcode() is either ISD::ADD, ISD::PTRADD, or ISD::SUB.
29842984
Known = KnownBits::computeForAddSub(
2985-
Op->isAnyAdd(), Flags.hasNoSignedWrap(), Flags.hasNoUnsignedWrap(),
2986-
KnownOp0, KnownOp1);
2985+
Op.getOpcode() != ISD::SUB, Flags.hasNoSignedWrap(),
2986+
Flags.hasNoUnsignedWrap(), KnownOp0, KnownOp1);
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}
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break;
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}

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2495,7 +2495,7 @@ bool AMDGPUDAGToDAGISel::SelectSMRDBaseOffset(SDNode *N, SDValue Addr,
24952495

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SDValue N0, N1;
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// Extract the base and offset if possible.
2498-
if (CurDAG->isBaseWithConstantOffset(Addr) || Addr->isAnyAdd()) {
2498+
if (Addr->isAnyAdd() || CurDAG->isADDLike(Addr)) {
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N0 = Addr.getOperand(0);
25002500
N1 = Addr.getOperand(1);
25012501
} else if (getBaseWithOffsetUsingSplitOR(*CurDAG, Addr, N0, N1)) {

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