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arsenmarsenm
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new triple checks
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9 files changed

+42
-40
lines changed

9 files changed

+42
-40
lines changed

‎llvm/include/llvm/TargetParser/Triple.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1103,6 +1103,12 @@ class Triple {
11031103
return getArch() == Triple::x86 || getArch() == Triple::x86_64;
11041104
}
11051105

1106+
/// Tests whether the target is x86 (32-bit).
1107+
bool isX86_32() const { return getArch() == Triple::x86; }
1108+
1109+
/// Tests whether the target is x86 (64-bit).
1110+
bool isX86_64() const { return getArch() == Triple::x86_64; }
1111+
11061112
/// Tests whether the target is VE
11071113
bool isVE() const {
11081114
return getArch() == Triple::ve;

‎llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -559,7 +559,7 @@ void X86AsmBackend::emitInstructionEnd(MCObjectStreamer &OS,
559559
std::optional<MCFixupKind> X86AsmBackend::getFixupKind(StringRef Name) const {
560560
if (STI.getTargetTriple().isOSBinFormatELF()) {
561561
unsigned Type;
562-
if (STI.getTargetTriple().getArch() == Triple::x86_64) {
562+
if (STI.getTargetTriple().isX86_64()) {
563563
Type = llvm::StringSwitch<unsigned>(Name)
564564
#define ELF_RELOC(X, Y) .Case(#X, Y)
565565
#include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
@@ -1286,7 +1286,7 @@ class DarwinX86AsmBackend : public X86AsmBackend {
12861286
DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI,
12871287
const MCSubtargetInfo &STI)
12881288
: X86AsmBackend(T, STI), MRI(MRI), TT(STI.getTargetTriple()),
1289-
Is64Bit(TT.getArch() == Triple::x86_64) {
1289+
Is64Bit(TT.isX86_64()) {
12901290
memset(SavedRegs, 0, sizeof(SavedRegs));
12911291
OffsetSize = Is64Bit ? 8 : 4;
12921292
MoveInstrSize = Is64Bit ? 3 : 2;

‎llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ const MCAsmInfo::AtSpecifier atSpecifiers[] = {
6868
void X86MCAsmInfoDarwin::anchor() { }
6969

7070
X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &T) {
71-
bool is64Bit = T.getArch() == Triple::x86_64;
71+
bool is64Bit = T.isX86_64();
7272
if (is64Bit)
7373
CodePointerSize = CalleeSaveStackSlotSize = 8;
7474

@@ -113,7 +113,7 @@ X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const Triple &Triple)
113113
void X86ELFMCAsmInfo::anchor() { }
114114

115115
X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) {
116-
bool is64Bit = T.getArch() == Triple::x86_64;
116+
bool is64Bit = T.isX86_64();
117117
bool isX32 = T.isX32();
118118

119119
// For ELF, x86-64 pointer size depends on the ABI.
@@ -149,7 +149,7 @@ X86_64MCAsmInfoDarwin::getExprForPersonalitySymbol(const MCSymbol *Sym,
149149
void X86MCAsmInfoMicrosoft::anchor() { }
150150

151151
X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const Triple &Triple) {
152-
if (Triple.getArch() == Triple::x86_64) {
152+
if (Triple.isX86_64()) {
153153
PrivateGlobalPrefix = ".L";
154154
PrivateLabelPrefix = ".L";
155155
CodePointerSize = 8;
@@ -189,7 +189,7 @@ void X86MCAsmInfoGNUCOFF::anchor() { }
189189
X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const Triple &Triple) {
190190
assert((Triple.isOSWindows() || Triple.isUEFI()) &&
191191
"Windows and UEFI are the only supported COFF targets");
192-
if (Triple.getArch() == Triple::x86_64) {
192+
if (Triple.isX86_64()) {
193193
PrivateGlobalPrefix = ".L";
194194
PrivateLabelPrefix = ".L";
195195
CodePointerSize = 8;

‎llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ std::string X86_MC::ParseX86Triple(const Triple &TT) {
4848
std::string FS;
4949
// SSE2 should default to enabled in 64-bit mode, but can be turned off
5050
// explicitly.
51-
if (TT.getArch() == Triple::x86_64)
51+
if (TT.isX86_64())
5252
FS = "+64bit-mode,-32bit-mode,-16bit-mode,+sse2";
5353
else if (TT.getEnvironment() != Triple::CODE16)
5454
FS = "-64bit-mode,+32bit-mode,-16bit-mode";
@@ -59,7 +59,7 @@ std::string X86_MC::ParseX86Triple(const Triple &TT) {
5959
}
6060

6161
unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
62-
if (TT.getArch() == Triple::x86_64)
62+
if (TT.isX86_64())
6363
return DWARFFlavour::X86_64;
6464

6565
if (TT.isOSDarwin())
@@ -407,9 +407,8 @@ static MCInstrInfo *createX86MCInstrInfo() {
407407
}
408408

409409
static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
410-
unsigned RA = (TT.getArch() == Triple::x86_64)
411-
? X86::RIP // Should have dwarf #16.
412-
: X86::EIP; // Should have dwarf #8.
410+
unsigned RA = TT.isX86_64() ? X86::RIP // Should have dwarf #16.
411+
: X86::EIP; // Should have dwarf #8.
413412

414413
MCRegisterInfo *X = new MCRegisterInfo();
415414
InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
@@ -421,7 +420,7 @@ static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
421420
static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
422421
const Triple &TheTriple,
423422
const MCTargetOptions &Options) {
424-
bool is64Bit = TheTriple.getArch() == Triple::x86_64;
423+
bool is64Bit = TheTriple.isX86_64();
425424

426425
MCAsmInfo *MAI;
427426
if (TheTriple.isOSBinFormatMachO()) {

‎llvm/lib/Target/X86/X86AsmPrinter.cpp‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -194,7 +194,7 @@ void X86AsmPrinter::emitKCFITypeId(const MachineFunction &MF) {
194194
if (F.getParent()->getModuleFlag("kcfi-arity")) {
195195
// The ArityToRegMap assumes the 64-bit SysV ABI.
196196
[[maybe_unused]] const auto &Triple = MF.getTarget().getTargetTriple();
197-
assert(Triple.getArch() == Triple::x86_64 && !Triple.isOSWindows());
197+
assert(Triple.isX86_64() && !Triple.isOSWindows());
198198

199199
// Determine the function's arity (i.e., the number of arguments) at the ABI
200200
// level by counting the number of parameters that are passed
@@ -897,16 +897,15 @@ void X86AsmPrinter::emitStartOfAsmFile(Module &M) {
897897

898898
if (FeatureFlagsAnd) {
899899
// Emit a .note.gnu.property section with the flags.
900-
assert((TT.isArch32Bit() || TT.getArch() == Triple::x86_64) &&
900+
assert((TT.isX86_32() || TT.isX86_64()) &&
901901
"CFProtection used on invalid architecture!");
902902
MCSection *Cur = OutStreamer->getCurrentSectionOnly();
903903
MCSection *Nt = MMI->getContext().getELFSection(
904904
".note.gnu.property", ELF::SHT_NOTE, ELF::SHF_ALLOC);
905905
OutStreamer->switchSection(Nt);
906906

907907
// Emitting note header.
908-
const int WordSize =
909-
TT.getArch() == Triple::x86_64 && !TT.isX32() ? 8 : 4;
908+
const int WordSize = TT.isX86_64() && !TT.isX32() ? 8 : 4;
910909
emitAlignment(WordSize == 4 ? Align(4) : Align(8));
911910
OutStreamer->emitIntValue(4, 4 /*size*/); // data size for "GNU\0"
912911
OutStreamer->emitIntValue(8 + WordSize, 4 /*size*/); // Elf_Prop size
@@ -1090,7 +1089,7 @@ void X86AsmPrinter::emitEndOfAsmFile(Module &M) {
10901089
}
10911090

10921091
// Emit __morestack address if needed for indirect calls.
1093-
if (TT.getArch() == Triple::x86_64 && TM.getCodeModel() == CodeModel::Large) {
1092+
if (TT.isX86_64() && TM.getCodeModel() == CodeModel::Large) {
10941093
if (MCSymbol *AddrSymbol = OutContext.lookupSymbol("__morestack_addr")) {
10951094
Align Alignment(1);
10961095
MCSection *ReadOnlySection = getObjFileLowering().getSectionForConstant(

‎llvm/lib/Target/X86/X86IndirectThunks.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -115,7 +115,7 @@ bool RetpolineThunkInserter::insertThunks(MachineModuleInfo &MMI,
115115
bool ExistingThunks) {
116116
if (ExistingThunks)
117117
return false;
118-
if (MMI.getTarget().getTargetTriple().getArch() == Triple::x86_64)
118+
if (MMI.getTarget().getTargetTriple().isX86_64())
119119
createThunkFunction(MMI, R11RetpolineName);
120120
else
121121
for (StringRef Name : {EAXRetpolineName, ECXRetpolineName, EDXRetpolineName,
@@ -125,7 +125,7 @@ bool RetpolineThunkInserter::insertThunks(MachineModuleInfo &MMI,
125125
}
126126

127127
void RetpolineThunkInserter::populateThunk(MachineFunction &MF) {
128-
bool Is64Bit = MF.getTarget().getTargetTriple().getArch() == Triple::x86_64;
128+
bool Is64Bit = MF.getTarget().getTargetTriple().isX86_64();
129129
Register ThunkReg;
130130
if (Is64Bit) {
131131
assert(MF.getName() == "__llvm_retpoline_r11" &&

‎llvm/lib/Target/X86/X86RegisterInfo.cpp‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -53,15 +53,14 @@ static cl::opt<bool>
5353
extern cl::opt<bool> X86EnableAPXForRelocation;
5454

5555
X86RegisterInfo::X86RegisterInfo(const Triple &TT)
56-
: X86GenRegisterInfo(
57-
(TT.getArch() == Triple::x86_64 ? X86::RIP : X86::EIP),
58-
X86_MC::getDwarfRegFlavour(TT, false),
59-
X86_MC::getDwarfRegFlavour(TT, true),
60-
(TT.getArch() == Triple::x86_64 ? X86::RIP : X86::EIP)) {
56+
: X86GenRegisterInfo((TT.isX86_64() ? X86::RIP : X86::EIP),
57+
X86_MC::getDwarfRegFlavour(TT, false),
58+
X86_MC::getDwarfRegFlavour(TT, true),
59+
(TT.isX86_64() ? X86::RIP : X86::EIP)) {
6160
X86_MC::initLLVMToSEHAndCVRegMapping(this);
6261

6362
// Cache some information.
64-
Is64Bit = TT.getArch() == Triple::x86_64;
63+
Is64Bit = TT.isX86_64();
6564
IsWin64 = Is64Bit && TT.isOSWindows();
6665
IsUEFI64 = Is64Bit && TT.isUEFI();
6766

‎llvm/lib/Target/X86/X86ReturnThunks.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ bool X86ReturnThunks::runOnMachineFunction(MachineFunction &MF) {
6868
return Modified;
6969

7070
const auto &ST = MF.getSubtarget<X86Subtarget>();
71-
const bool Is64Bit = ST.getTargetTriple().getArch() == Triple::x86_64;
71+
const bool Is64Bit = ST.getTargetTriple().isX86_64();
7272
const unsigned RetOpc = Is64Bit ? X86::RET64 : X86::RET32;
7373
SmallVector<MachineInstr *, 16> Rets;
7474

‎llvm/lib/Target/X86/X86TargetMachine.cpp‎

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -112,15 +112,15 @@ extern "C" LLVM_C_ABI void LLVMInitializeX86Target() {
112112

113113
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
114114
if (TT.isOSBinFormatMachO()) {
115-
if (TT.getArch() == Triple::x86_64)
115+
if (TT.isX86_64())
116116
return std::make_unique<X86_64MachoTargetObjectFile>();
117117
return std::make_unique<TargetLoweringObjectFileMachO>();
118118
}
119119

120120
if (TT.isOSBinFormatCOFF())
121121
return std::make_unique<TargetLoweringObjectFileCOFF>();
122122

123-
if (TT.getArch() == Triple::x86_64)
123+
if (TT.isX86_64())
124124
return std::make_unique<X86_64ELFTargetObjectFile>();
125125
return std::make_unique<X86ELFTargetObjectFile>();
126126
}
@@ -131,7 +131,7 @@ static std::string computeDataLayout(const Triple &TT) {
131131

132132
Ret += DataLayout::getManglingComponent(TT);
133133
// X86 and x32 have 32 bit pointers.
134-
if (TT.getArch() != Triple::x86_64 || TT.isX32())
134+
if (TT.isX86_32() || TT.isX32())
135135
Ret += "-p:32:32";
136136

137137
// Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
@@ -140,7 +140,7 @@ static std::string computeDataLayout(const Triple &TT) {
140140
// Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
141141
// 128 bit integers are not specified in the 32-bit ABIs but are used
142142
// internally for lowering f128, so we match the alignment to that.
143-
if (TT.getArch() == Triple::x86_64 || TT.isOSWindows())
143+
if (TT.isX86_64() || TT.isOSWindows())
144144
Ret += "-i64:64-i128:128";
145145
else if (TT.isOSIAMCU())
146146
Ret += "-i64:32-f64:32";
@@ -150,8 +150,7 @@ static std::string computeDataLayout(const Triple &TT) {
150150
// Some ABIs align long double to 128 bits, others to 32.
151151
if (TT.isOSIAMCU())
152152
; // No f80
153-
else if (TT.getArch() == Triple::x86_64 || TT.isOSDarwin() ||
154-
TT.isWindowsMSVCEnvironment())
153+
else if (TT.isX86_64() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
155154
Ret += "-f80:128";
156155
else
157156
Ret += "-f80:32";
@@ -160,13 +159,13 @@ static std::string computeDataLayout(const Triple &TT) {
160159
Ret += "-f128:32";
161160

162161
// The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
163-
if (TT.getArch() == Triple::x86_64)
162+
if (TT.isX86_64())
164163
Ret += "-n8:16:32:64";
165164
else
166165
Ret += "-n8:16:32";
167166

168167
// The stack is aligned to 32 bits on some ABIs and 128 bits on others.
169-
if ((TT.getArch() != Triple::x86_64 && TT.isOSWindows()) || TT.isOSIAMCU())
168+
if ((TT.isX86_32() && TT.isOSWindows()) || TT.isOSIAMCU())
170169
Ret += "-a:0:32-S32";
171170
else
172171
Ret += "-S128";
@@ -176,7 +175,7 @@ static std::string computeDataLayout(const Triple &TT) {
176175

177176
static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT,
178177
std::optional<Reloc::Model> RM) {
179-
bool is64Bit = TT.getArch() == Triple::x86_64;
178+
bool is64Bit = TT.isX86_64();
180179
if (!RM) {
181180
// JIT codegen should use static relocations by default, since it's
182181
// typically executed in process and not relocatable.
@@ -218,7 +217,7 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT,
218217
static CodeModel::Model
219218
getEffectiveX86CodeModel(const Triple &TT, std::optional<CodeModel::Model> CM,
220219
bool JIT) {
221-
bool Is64Bit = TT.getArch() == Triple::x86_64;
220+
bool Is64Bit = TT.isX86_64();
222221
if (CM) {
223222
if (*CM == CodeModel::Tiny)
224223
reportFatalUsageError("target does not support the tiny CodeModel");
@@ -489,7 +488,7 @@ void X86PassConfig::addIRPasses() {
489488
// Add Control Flow Guard checks.
490489
const Triple &TT = TM->getTargetTriple();
491490
if (TT.isOSWindows()) {
492-
if (TT.getArch() == Triple::x86_64) {
491+
if (TT.isX86_64()) {
493492
addPass(createCFGuardDispatchPass());
494493
} else {
495494
addPass(createCFGuardCheckPass());
@@ -548,7 +547,7 @@ bool X86PassConfig::addILPOpts() {
548547
bool X86PassConfig::addPreISel() {
549548
// Only add this pass for 32-bit x86 Windows.
550549
const Triple &TT = TM->getTargetTriple();
551-
if (TT.isOSWindows() && TT.getArch() == Triple::x86)
550+
if (TT.isOSWindows() && TT.isX86_32())
552551
addPass(createX86WinEHStatePass());
553552
return true;
554553
}
@@ -637,7 +636,7 @@ void X86PassConfig::addPreEmitPass2() {
637636

638637
// Insert extra int3 instructions after trailing call instructions to avoid
639638
// issues in the unwinder.
640-
if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
639+
if (TT.isOSWindows() && TT.isX86_64())
641640
addPass(createX86AvoidTrailingCallPass());
642641

643642
// Verify basic block incoming and outgoing cfa offset and register values and
@@ -674,7 +673,7 @@ void X86PassConfig::addPreEmitPass2() {
674673

675674
// Analyzes and emits pseudos to support Win x64 Unwind V2. This pass must run
676675
// after all real instructions have been added to the epilog.
677-
if (TT.isOSWindows() && (TT.getArch() == Triple::x86_64))
676+
if (TT.isOSWindows() && TT.isX86_64())
678677
addPass(createX86WinEHUnwindV2Pass());
679678
}
680679

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