Added the mips extension instructions like ehb,ihb and pause etc.

ukalappa-mips · ukalappa-mips · commit 7dca481baec6 · 2025-08-28T04:53:00.000Z
Please refer the https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf for more information . and files like RISCVInstrInfoXMips.td clang formatted . No Regression found.
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -656,6 +656,13 @@ static constexpr FeatureBitset XSfSystemGroup = {
     RISCV::FeatureVendorXSiFivecflushdlone,
 };
 
+static constexpr FeatureBitset XMIPSGroup = {
+    RISCV::FeatureVendorXMIPSLSP,
+    RISCV::FeatureVendorXMIPSCMov,
+    RISCV::FeatureVendorXMIPSCBOP,
+    RISCV::FeatureVendorXMIPSEXECTL,
+};
+
 static constexpr FeatureBitset XTHeadGroup = {
     RISCV::FeatureVendorXTHeadBa,      RISCV::FeatureVendorXTHeadBb,
     RISCV::FeatureVendorXTHeadBs,      RISCV::FeatureVendorXTHeadCondMov,
@@ -684,13 +691,7 @@ static constexpr DecoderListEntry DecoderList32[]{
     {DecoderTableXSfvector32, XSfVectorGroup, "SiFive vector extensions"},
     {DecoderTableXSfsystem32, XSfSystemGroup, "SiFive system extensions"},
     {DecoderTableXSfcease32, {RISCV::FeatureVendorXSfcease}, "SiFive sf.cease"},
-    {DecoderTableXmipslsp32, {RISCV::FeatureVendorXMIPSLSP}, "MIPS mips.lsp"},
-    {DecoderTableXmipscmov32,
-     {RISCV::FeatureVendorXMIPSCMov},
-     "MIPS mips.ccmov"},
-    {DecoderTableXmipscbop32,
-     {RISCV::FeatureVendorXMIPSCBOP},
-     "MIPS mips.pref"},
+    {DecoderTableXMIPS32, XMIPSGroup, "Mips extensions"},
     {DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
     {DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
     // Standard Extensions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1396,20 +1396,27 @@ def HasVendorXMIPSCMov
       AssemblerPredicate<(all_of FeatureVendorXMIPSCMov),
                          "'Xmipscmov' ('mips.ccmov' instruction)">;
 def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
+
 def FeatureVendorXMIPSLSP
     : RISCVExtension<1, 0, "MIPS optimization for hardware load-store bonding">;
 def HasVendorXMIPSLSP
     : Predicate<"Subtarget->hasVendorXMIPSLSP()">,
       AssemblerPredicate<(all_of FeatureVendorXMIPSLSP),
                          "'Xmipslsp' (load and store pair instructions)">;
-def FeatureVendorXMIPSCBOP
-    : RISCVExtension<1, 0, "MIPS Software Prefetch">;
+
+def FeatureVendorXMIPSCBOP : RISCVExtension<1, 0, "MIPS Software Prefetch">;
 def HasVendorXMIPSCBOP
     : Predicate<"Subtarget->hasVendorXMIPSCBOP()">,
       AssemblerPredicate<(all_of FeatureVendorXMIPSCBOP),
                          "'Xmipscbop' (MIPS hardware prefetch)">;
 def NoVendorXMIPSCBOP : Predicate<"!Subtarget->hasVendorXMIPSCBOP()">;
 
+def FeatureVendorXMIPSEXECTL : RISCVExtension<1, 0, "MIPS extensions">;
+def HasVendorXMIPSEXECTL
+    : Predicate<"Subtarget->hasVendorXMIPSEXT()">,
+      AssemblerPredicate<(all_of FeatureVendorXMIPSEXECTL),
+                         "'Xmipsexectl' (Mips extensions)">;
+
 // WCH / Nanjing Qinheng Microelectronics Extension(s)
 
 def FeatureVendorXwchc
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
@@ -47,13 +47,13 @@ class LDPFormat<dag outs, dag ins, string opcodestr, string argstr>
   bits<5> rd1;
   bits<5> rd2;
 
-  let Inst{31-27} = rd2;
-  let Inst{26-23} = imm7{6-3};
-  let Inst{22-20} = 0b000;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = 0b100;
-  let Inst{11-7} = rd1;
-  let Inst{6-0} = OPC_CUSTOM_0.Value;
+  let Inst{31 - 27} = rd2;
+  let Inst{26 - 23} = imm7{6 - 3};
+  let Inst{22 - 20} = 0b000;
+  let Inst{19 - 15} = rs1;
+  let Inst{14 - 12} = 0b100;
+  let Inst{11 - 7} = rd1;
+  let Inst{6 - 0} = OPC_CUSTOM_0.Value;
 }
 
 // Load word pair format.
@@ -64,13 +64,13 @@ class LWPFormat<dag outs, dag ins, string opcodestr, string argstr>
   bits<5> rd1;
   bits<5> rd2;
 
-  let Inst{31-27} = rd2;
-  let Inst{26-22} = imm7{6-2};
-  let Inst{21-20} = 0b01;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = 0b100;
-  let Inst{11-7} = rd1;
-  let Inst{6-0} = OPC_CUSTOM_0.Value;
+  let Inst{31 - 27} = rd2;
+  let Inst{26 - 22} = imm7{6 - 2};
+  let Inst{21 - 20} = 0b01;
+  let Inst{19 - 15} = rs1;
+  let Inst{14 - 12} = 0b100;
+  let Inst{11 - 7} = rd1;
+  let Inst{6 - 0} = OPC_CUSTOM_0.Value;
 }
 
 // Store double pair format.
@@ -81,14 +81,14 @@ class SDPFormat<dag outs, dag ins, string opcodestr, string argstr>
   bits<5> rs2;
   bits<5> rs1;
 
-  let Inst{31-27} = rs3;
-  let Inst{26-25} = imm7{6-5};
-  let Inst{24-20} = rs2;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = 0b101;
-  let Inst{11-10} = imm7{4-3};
-  let Inst{9-7} = 0b000;
-  let Inst{6-0} = OPC_CUSTOM_0.Value;
+  let Inst{31 - 27} = rs3;
+  let Inst{26 - 25} = imm7{6 - 5};
+  let Inst{24 - 20} = rs2;
+  let Inst{19 - 15} = rs1;
+  let Inst{14 - 12} = 0b101;
+  let Inst{11 - 10} = imm7{4 - 3};
+  let Inst{9 - 7} = 0b000;
+  let Inst{6 - 0} = OPC_CUSTOM_0.Value;
 }
 
 // Store word pair format.
@@ -99,89 +99,167 @@ class SWPFormat<dag outs, dag ins, string opcodestr, string argstr>
   bits<5> rs2;
   bits<5> rs1;
 
-  let Inst{31-27} = rs3;
-  let Inst{26-25} = imm7{6-5};
-  let Inst{24-20} = rs2;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = 0b101;
-  let Inst{11-9} = imm7{4-2};
-  let Inst{8-7} = 0b01;
-  let Inst{6-0} = OPC_CUSTOM_0.Value;
+  let Inst{31 - 27} = rs3;
+  let Inst{26 - 25} = imm7{6 - 5};
+  let Inst{24 - 20} = rs2;
+  let Inst{19 - 15} = rs1;
+  let Inst{14 - 12} = 0b101;
+  let Inst{11 - 9} = imm7{4 - 2};
+  let Inst{8 - 7} = 0b01;
+  let Inst{6 - 0} = OPC_CUSTOM_0.Value;
 }
 
 // Prefetch format.
-let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
-class Mips_prefetch_ri<dag outs, dag ins, string opcodestr, string argstr>
+let hasSideEffects = 0, mayLoad = 1,
+    mayStore = 1 in class
+        Mips_prefetch_ri<dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
   bits<9> imm9;
   bits<5> rs1;
   bits<5> hint;
 
-  let Inst{31-29} = 0b000;
-  let Inst{28-20} = imm9;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = 0b000;
-  let Inst{11-7} = hint;
-  let Inst{6-0} = OPC_CUSTOM_0.Value;
+  let Inst{31 - 29} = 0b000;
+  let Inst{28 - 20} = imm9;
+  let Inst{19 - 15} = rs1;
+  let Inst{14 - 12} = 0b000;
+  let Inst{11 - 7} = hint;
+  let Inst{6 - 0} = OPC_CUSTOM_0.Value;
+}
+
+// MIPS Ext Insns
+let hasSideEffects = 1, mayLoad = 0,
+    mayStore = 0 in class MIPSExtInst_ri<bits<6> shimm5, string opcodestr>
+    : RVInstIShift<0b00000, 0b001, OPC_OP_IMM, (outs), (ins), opcodestr, ""> {
+  let shamt = shimm5;
+  let rd = 0;
+  let rs1 = 0;
 }
 
 //===----------------------------------------------------------------------===//
 // MIPS extensions
 //===----------------------------------------------------------------------===//
-let Predicates = [HasVendorXMIPSCBOP] ,DecoderNamespace = "Xmipscbop" in {
-  def MIPS_PREF : Mips_prefetch_ri<(outs), (ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
-                                    "mips.pref", "$hint, ${imm9}(${rs1})">,
-                   Sched<[]>;
+let Predicates = [HasVendorXMIPSCBOP], DecoderNamespace = "XMIPS" in {
+  def MIPS_PREF : Mips_prefetch_ri<(outs),
+                                   (ins GPR
+                                    : $rs1, uimm9
+                                    : $imm9, uimm5
+                                    : $hint),
+                                   "mips.pref", "$hint, ${imm9}(${rs1})">,
+                  Sched<[]>;
+}
+
+let Predicates = [HasVendorXMIPSEXECTL], DecoderNamespace = "XMIPS" in {
+  def MIPS_EHB : MIPSExtInst_ri<0b000011, "mips.ehb">;
+  def MIPS_IHB : MIPSExtInst_ri<0b000001, "mips.ihb">;
+  def MIPS_PAUSE : MIPSExtInst_ri<0b000101, "mips.pause">;
 }
 
 let Predicates = [HasVendorXMIPSCBOP] in {
   // Prefetch Data Write.
-  def : Pat<(prefetch (AddrRegImm9  (XLenVT GPR:$rs1), uimm9:$imm9),
+  def : Pat<(prefetch(AddrRegImm9(XLenVT GPR
+                                  : $rs1),
+                      uimm9
+                      : $imm9),
              (i32 1), timm, (i32 1)),
-            (MIPS_PREF GPR:$rs1, uimm9:$imm9, 9)>;
+            (MIPS_PREF GPR
+             : $rs1, uimm9
+             : $imm9, 9)>;
   // Prefetch Data Read.
-  def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),
+  def : Pat<(prefetch(AddrRegImm9(XLenVT GPR
+                                  : $rs1),
+                      uimm9
+                      : $imm9),
              (i32 0), timm, (i32 1)),
-            (MIPS_PREF GPR:$rs1, uimm9:$imm9, 8)>;
+            (MIPS_PREF GPR
+             : $rs1, uimm9
+             : $imm9, 8)>;
 }
 
-let Predicates = [HasVendorXMIPSCMov], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
-                 DecoderNamespace = "Xmipscmov" in {
-def MIPS_CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
-                          (ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
-                          "mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
-                 Sched<[]>;
+let Predicates = [HasVendorXMIPSCMov], hasSideEffects = 0, mayLoad = 0,
+    mayStore = 0, DecoderNamespace = "XMIPS" in {
+  def MIPS_CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0,
+                            (outs GPR
+                             : $rd),
+                            (ins GPR
+                             : $rs1, GPR
+                             : $rs2, GPR
+                             : $rs3),
+                            "mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
+                   Sched<[]>;
 }
 
 let Predicates = [UseCCMovInsn] in {
-def : Pat<(select (riscv_setne (XLenVT GPR:$rs2)),
-                  (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
-          (MIPS_CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(select (riscv_seteq (XLenVT GPR:$rs2)),
-                  (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
-          (MIPS_CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-
-def : Pat<(select (XLenVT GPR:$rs2), (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
-          (MIPS_CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+  def : Pat<(select(riscv_setne(XLenVT GPR
+                                : $rs2)),
+             (XLenVT GPR
+              : $rs1),
+             (XLenVT GPR
+              : $rs3)),
+            (MIPS_CCMOV GPR
+             : $rs1, GPR
+             : $rs2, GPR
+             : $rs3)>;
+  def : Pat<(select(riscv_seteq(XLenVT GPR
+                                : $rs2)),
+             (XLenVT GPR
+              : $rs3),
+             (XLenVT GPR
+              : $rs1)),
+            (MIPS_CCMOV GPR
+             : $rs1, GPR
+             : $rs2, GPR
+             : $rs3)>;
+
+  def : Pat<(select(XLenVT GPR
+                    : $rs2),
+             (XLenVT GPR
+              : $rs1),
+             (XLenVT GPR
+              : $rs3)),
+            (MIPS_CCMOV GPR
+             : $rs1, GPR
+             : $rs2, GPR
+             : $rs3)>;
 }
 
 let Predicates = [HasVendorXMIPSLSP], hasSideEffects = 0,
-                 DecoderNamespace = "Xmipslsp" in {
-let mayLoad = 1, mayStore = 0 in {
-def MIPS_LWP : LWPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1, uimm7_lsb00:$imm7),
-                         "mips.lwp", "$rd1, $rd2, ${imm7}(${rs1})">,
-               Sched<[WriteLDW, WriteLDW, ReadMemBase]>;
-def MIPS_LDP : LDPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1, uimm7_lsb000:$imm7),
-                         "mips.ldp", "$rd1, $rd2, ${imm7}(${rs1})">,
-               Sched<[WriteLDD, WriteLDD, ReadMemBase]>;
-} // mayLoad = 1, mayStore = 0
-
-let mayLoad = 0, mayStore = 1 in {
-def MIPS_SWP : SWPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1, uimm7_lsb00:$imm7),
-                         "mips.swp", "$rs2, $rs3, ${imm7}(${rs1})">,
-               Sched<[WriteSTW, ReadStoreData, ReadStoreData, ReadMemBase]>;
-def MIPS_SDP : SDPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1, uimm7_lsb000:$imm7),
-                         "mips.sdp", "$rs2, $rs3, ${imm7}(${rs1})">,
-               Sched<[WriteSTD, ReadStoreData, ReadStoreData, ReadMemBase]>;
-} // mayLoad = 0, mayStore = 1
-} // Predicates = [HasVendorXMIPSLSP], hasSideEffects = 0, DecoderNamespace = "Xmipslsp"
+    DecoderNamespace = "XMIPS" in {
+  let mayLoad = 1, mayStore = 0 in {
+    def MIPS_LWP : LWPFormat<(outs GPR
+                              : $rd1, GPR
+                              : $rd2),
+                             (ins GPR
+                              : $rs1, uimm7_lsb00
+                              : $imm7),
+                             "mips.lwp", "$rd1, $rd2, ${imm7}(${rs1})">,
+                   Sched<[WriteLDW, WriteLDW, ReadMemBase]>;
+    def MIPS_LDP : LDPFormat<(outs GPR
+                              : $rd1, GPR
+                              : $rd2),
+                             (ins GPR
+                              : $rs1, uimm7_lsb000
+                              : $imm7),
+                             "mips.ldp", "$rd1, $rd2, ${imm7}(${rs1})">,
+                   Sched<[WriteLDD, WriteLDD, ReadMemBase]>;
+  } // mayLoad = 1, mayStore = 0
+
+  let mayLoad = 0, mayStore = 1 in {
+    def MIPS_SWP : SWPFormat<(outs),
+                             (ins GPR
+                              : $rs2, GPR
+                              : $rs3, GPR
+                              : $rs1, uimm7_lsb00
+                              : $imm7),
+                             "mips.swp", "$rs2, $rs3, ${imm7}(${rs1})">,
+                   Sched<[WriteSTW, ReadStoreData, ReadStoreData, ReadMemBase]>;
+    def MIPS_SDP : SDPFormat<(outs),
+                             (ins GPR
+                              : $rs2, GPR
+                              : $rs3, GPR
+                              : $rs1, uimm7_lsb000
+                              : $imm7),
+                             "mips.sdp", "$rs2, $rs3, ${imm7}(${rs1})">,
+                   Sched<[WriteSTD, ReadStoreData, ReadStoreData, ReadMemBase]>;
+  } // mayLoad = 0, mayStore = 1
+} // Predicates = [HasVendorXMIPSLSP], hasSideEffects = 0, DecoderNamespace =
+  // "XMIPS"
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -121,7 +121,8 @@ def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
                                       FeatureStdExtZicsr,
                                       FeatureVendorXMIPSCMov,
                                       FeatureVendorXMIPSLSP,
-                                      FeatureVendorXMIPSCBOP],
+                                      FeatureVendorXMIPSCBOP,
+				      FeatureVendorXMIPSEXECTL],
                                      [TuneMIPSP8700]>;
 
 def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -198,6 +198,7 @@
 ; CHECK-NEXT:   xcvsimd                          - 'XCVsimd' (CORE-V SIMD ALU).
 ; CHECK-NEXT:   xmipscbop                        - 'XMIPSCBOP' (MIPS Software Prefetch).
 ; CHECK-NEXT:   xmipscmov                        - 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov)).
+; CHECK-NEXT:   mipsexectl                       - 'XMIPSEXECTL' (MIPS extensions).
 ; CHECK-NEXT:   xmipslsp                         - 'XMIPSLSP' (MIPS optimization for hardware load-store bonding).
 ; CHECK-NEXT:   xsfcease                         - 'XSfcease' (SiFive sf.cease Instruction).
 ; CHECK-NEXT:   xsfmm128t                        - 'XSfmm128t' (TE=128 configuration).
diff --git a/llvm/test/MC/RISCV/xmips-invalid.s b/llvm/test/MC/RISCV/xmips-invalid.s
@@ -1,5 +1,14 @@
 # RUN: not llvm-mc -triple=riscv64 < %s 2>&1 | FileCheck %s -check-prefixes=CHECK-FEATURE
-# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+Xmipscbop < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop,+xmipsexectl < %s 2>&1 | FileCheck %s
+
+mips.pause 10
+# CHECK: error: invalid operand for instruction
+
+mips.ehb 10
+# CHECK: error: invalid operand for instruction 
+
+mips.ihb 10
+# CHECK: error: invalid operand for instruction
 
 mips.pref   8, 512(a0)
 # CHECK: error: immediate offset must be in the range [0, 511]
diff --git a/llvm/test/MC/RISCV/xmips-valid.s b/llvm/test/MC/RISCV/xmips-valid.s
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
