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fhossein-quicfhossein-quic
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formatting + remove undef
1 parent 3f1794c commit 753cffd

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2 files changed

+28
-30
lines changed

2 files changed

+28
-30
lines changed

‎llvm/lib/Target/Hexagon/HexagonQFPoptimizer.cpp‎

Lines changed: 22 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -84,8 +84,7 @@ using namespace llvm;
8484

8585
cl::opt<bool>
8686
DisableQFOptimizer("disable-qfp-opt", cl::init(false),
87-
cl::desc(
88-
"Disable optimization of Qfloat operations."));
87+
cl::desc("Disable optimization of Qfloat operations."));
8988

9089
std::vector<unsigned short> QFPInst = {
9190
Hexagon::V6_vadd_hf, Hexagon::V6_vadd_qf16,
@@ -173,8 +172,8 @@ bool HexagonQFPoptimizer::optimizeQfp(MachineInstr *MI,
173172
MachineOperand &Res = MI->getOperand(0);
174173
MachineInstr *Inst1 = nullptr;
175174
MachineInstr *Inst2 = nullptr;
176-
LLVM_DEBUG(dbgs() << "\n[Reaching Defs of operands]: ";
177-
DefMI1->dump(); DefMI2->dump());
175+
LLVM_DEBUG(dbgs() << "\n[Reaching Defs of operands]: "; DefMI1->dump();
176+
DefMI2->dump());
178177

179178
// Get the reaching defs of DefMI
180179
if (DefMI1->getNumOperands() > 1 && DefMI1->getOperand(1).isReg() &&
@@ -197,9 +196,9 @@ bool HexagonQFPoptimizer::optimizeQfp(MachineInstr *MI,
197196

198197
// If the reaching defs of DefMI are W register type, we return
199198
if ((Inst1 && MRI->getRegClass(Inst1->getOperand(0).getReg()) ==
200-
&Hexagon::HvxWRRegClass) || (Inst2 &&
201-
MRI->getRegClass(Inst2->getOperand(0).getReg()) ==
202-
&Hexagon::HvxWRRegClass))
199+
&Hexagon::HvxWRRegClass) ||
200+
(Inst2 && MRI->getRegClass(Inst2->getOperand(0).getReg()) ==
201+
&Hexagon::HvxWRRegClass))
203202
return false;
204203

205204
// Analyze the use operands of the conversion to get their KILL status
@@ -215,14 +214,13 @@ bool HexagonQFPoptimizer::optimizeQfp(MachineInstr *MI,
215214
if (MI->getOpcode() != Hexagon::V6_vmpy_qf32_sf)
216215
InstTy = QFPInstMap[QFPInstMap[MI->getOpcode()]];
217216

218-
MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
219-
HII->get(InstTy), Res.getReg())
220-
.addReg(Src1.getReg(), Op0F, Src1.getSubReg())
221-
.addReg(Src2.getReg(), Op1F, Src2.getSubReg());
217+
MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), HII->get(InstTy), Res.getReg())
218+
.addReg(Src1.getReg(), Op0F, Src1.getSubReg())
219+
.addReg(Src2.getReg(), Op1F, Src2.getSubReg());
222220
LLVM_DEBUG(dbgs() << "\n[Inserting]: "; MIB.getInstr()->dump());
223221
return true;
224222

225-
// Check if left operand's reaching def is a conversion to sf/hf
223+
// Check if left operand's reaching def is a conversion to sf/hf
226224
} else if (((Def1OP == Hexagon::V6_vconv_sf_qf32 &&
227225
Def2OP != Hexagon::V6_vconv_sf_qf32) ||
228226
(Def1OP == Hexagon::V6_vconv_hf_qf16 &&
@@ -231,7 +229,7 @@ bool HexagonQFPoptimizer::optimizeQfp(MachineInstr *MI,
231229
(MI->getOpcode() != Hexagon::V6_vmpy_qf32_sf)) {
232230

233231
if (Inst1 && MRI->getRegClass(Inst1->getOperand(0).getReg()) ==
234-
&Hexagon::HvxWRRegClass)
232+
&Hexagon::HvxWRRegClass)
235233
return false;
236234

237235
MachineOperand &Src1 = DefMI1->getOperand(1);
@@ -241,12 +239,12 @@ bool HexagonQFPoptimizer::optimizeQfp(MachineInstr *MI,
241239
Src1.setIsKill(false);
242240
Op1F = getKillRegState(Src2.isKill());
243241
MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), HII->get(InstTy), Res.getReg())
244-
.addReg(Src1.getReg(), Op0F, Src1.getSubReg())
245-
.addReg(Src2.getReg(), Op1F, Src2.getSubReg());
242+
.addReg(Src1.getReg(), Op0F, Src1.getSubReg())
243+
.addReg(Src2.getReg(), Op1F, Src2.getSubReg());
246244
LLVM_DEBUG(dbgs() << "\n[Inserting]: "; MIB.getInstr()->dump());
247245
return true;
248246

249-
// Check if right operand's reaching def is a conversion tp sf/hf
247+
// Check if right operand's reaching def is a conversion tp sf/hf
250248
} else if (((Def1OP != Hexagon::V6_vconv_sf_qf32 &&
251249
Def2OP == Hexagon::V6_vconv_sf_qf32) ||
252250
(Def1OP != Hexagon::V6_vconv_hf_qf16 &&
@@ -262,7 +260,7 @@ bool HexagonQFPoptimizer::optimizeQfp(MachineInstr *MI,
262260
return false;
263261

264262
if (Inst2 && MRI->getRegClass(Inst2->getOperand(0).getReg()) ==
265-
&Hexagon::HvxWRRegClass)
263+
&Hexagon::HvxWRRegClass)
266264
return false;
267265

268266
MachineOperand &Src1 = MI->getOperand(1);
@@ -272,9 +270,9 @@ bool HexagonQFPoptimizer::optimizeQfp(MachineInstr *MI,
272270
Src2.setIsKill(false);
273271
Op0F = getKillRegState(Src1.isKill());
274272
MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), HII->get(InstTy), Res.getReg())
275-
.addReg(Src2.getReg(), Op1F,
276-
Src2.getSubReg()) // Notice the operands are flipped.
277-
.addReg(Src1.getReg(), Op0F, Src1.getSubReg());
273+
.addReg(Src2.getReg(), Op1F,
274+
Src2.getSubReg()) // Notice the operands are flipped.
275+
.addReg(Src1.getReg(), Op0F, Src1.getSubReg());
278276
LLVM_DEBUG(dbgs() << "\n[Inserting]: "; MIB.getInstr()->dump());
279277
return true;
280278
}
@@ -297,8 +295,8 @@ bool HexagonQFPoptimizer::runOnMachineFunction(MachineFunction &MF) {
297295
MRI = &MF.getRegInfo();
298296

299297
MachineFunction::iterator MBBI = MF.begin();
300-
LLVM_DEBUG(dbgs() << "\n=== Running QFPOptimzer Pass for : " <<
301-
MF.getName() << " Optimize intermediate conversions ===\n");
298+
LLVM_DEBUG(dbgs() << "\n=== Running QFPOptimzer Pass for : " << MF.getName()
299+
<< " Optimize intermediate conversions ===\n");
302300
while (MBBI != MF.end()) {
303301
MachineBasicBlock *MBB = &*MBBI;
304302
MachineBasicBlock::iterator MII = MBBI->instr_begin();
@@ -309,13 +307,13 @@ bool HexagonQFPoptimizer::runOnMachineFunction(MachineFunction &MF) {
309307
if (llvm::find(QFPInst, MI->getOpcode()) != QFPInst.end())
310308
if (MI->getOpcode() != Hexagon::V6_vconv_sf_qf32 &&
311309
MI->getOpcode() != Hexagon::V6_vconv_hf_qf16) {
312-
LLVM_DEBUG(dbgs() << "\n###Analyzing for removal: ";MI->dump());
310+
LLVM_DEBUG(dbgs() << "\n###Analyzing for removal: "; MI->dump());
313311
if (optimizeQfp(MI, MBB)) {
314312
MI->eraseFromParent();
315313
LLVM_DEBUG(dbgs() << "\t....Removing....");
316314
Changed = true;
317315
}
318-
}
316+
}
319317
}
320318
++MBBI;
321319
}

‎llvm/test/CodeGen/Hexagon/qfp-conv.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10,13 +10,13 @@ entry:
1010
br label %for.body
1111

1212
for.body:
13-
%optr.068 = phi <32 x i32>* [ undef, %entry ], [ %incdec.ptr6, %for.body ]
14-
%0 = tail call <32 x i32> @llvm.hexagon.V6.vconv.hf.qf32.128B(<64 x i32> undef) #2
13+
%optr.068 = phi <32 x i32>* [ %ptr, %entry ], [ %incdec.ptr6, %for.body ]
14+
%0 = tail call <32 x i32> @llvm.hexagon.V6.vconv.hf.qf32.128B(<64 x i32> %input64) #2
1515
%1 = tail call <32 x i32> @llvm.hexagon.V6.vdealh.128B(<32 x i32> %0) #2
16-
%2 = tail call <128 x i1> @llvm.hexagon.V6.vgth.128B(<32 x i32> undef, <32 x i32> %1) #2
17-
%3 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1> %2, <32 x i32> undef, <32 x i32> undef) #2
18-
%4 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %3, <32 x i32> undef) #2
19-
%5 = tail call <32 x i32> @llvm.hexagon.V6.vpackhub.sat.128B(<32 x i32> undef, <32 x i32> %4) #2
16+
%2 = tail call <128 x i1> @llvm.hexagon.V6.vgth.128B(<32 x i32> %input32a, <32 x i32> %1) #2
17+
%3 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1> %2, <32 x i32> %input32b, <32 x i32> %input32c) #2
18+
%4 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %3, <32 x i32> %input32d) #2
19+
%5 = tail call <32 x i32> @llvm.hexagon.V6.vpackhub.sat.128B(<32 x i32> %input32e, <32 x i32> %4) #2
2020
store <32 x i32> %5, <32 x i32>* %optr.068, align 1
2121
%incdec.ptr6 = getelementptr inbounds <32 x i32>, <32 x i32>* %optr.068, i32 1
2222
br label %for.body

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