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fixup! introduce RISCVISD::INSERT_SUBVECTOR, RISCVISD::EXTRACT_SUBVECTOR and some minor changes
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7 files changed

+44
-56
lines changed

7 files changed

+44
-56
lines changed

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp‎

Lines changed: 11 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -7283,19 +7283,17 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
72837283
EVT N1VT = N1.getValueType();
72847284
assert(VT.isVector() && N1VT.isVector() &&
72857285
"Extract subvector VTs must be vectors!");
7286-
if (!N1VT.isRISCVVectorTuple())
7287-
assert(VT.getVectorElementType() == N1VT.getVectorElementType() &&
7288-
"Extract subvector VTs must have the same element type!");
7289-
assert((VT.isFixedLengthVector() || N1VT.isScalableVector() ||
7290-
N1VT.isRISCVVectorTuple()) &&
7286+
assert(VT.getVectorElementType() == N1VT.getVectorElementType() &&
7287+
"Extract subvector VTs must have the same element type!");
7288+
assert((VT.isFixedLengthVector() || N1VT.isScalableVector()) &&
72917289
"Cannot extract a scalable vector from a fixed length vector!");
72927290
assert((VT.isScalableVector() != N1VT.isScalableVector() ||
72937291
VT.getVectorMinNumElements() <= N1VT.getVectorMinNumElements()) &&
72947292
"Extract subvector must be from larger vector to smaller vector!");
72957293
assert(N2C && "Extract subvector index must be a constant");
72967294
assert((VT.isScalableVector() != N1VT.isScalableVector() ||
7297-
((N1VT.isRISCVVectorTuple() ? 0 : VT.getVectorMinNumElements()) +
7298-
N2C->getZExtValue()) <= N1VT.getVectorMinNumElements()) &&
7295+
(VT.getVectorMinNumElements() + N2C->getZExtValue()) <=
7296+
N1VT.getVectorMinNumElements()) &&
72997297
"Extract subvector overflow!");
73007298
assert(N2C->getAPIntValue().getBitWidth() ==
73017299
TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() &&
@@ -7518,23 +7516,18 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
75187516
"Dest and insert subvector source types must match!");
75197517
assert(VT.isVector() && N2VT.isVector() &&
75207518
"Insert subvector VTs must be vectors!");
7521-
if (!VT.isRISCVVectorTuple()) {
7522-
assert(VT.getVectorElementType() == N2VT.getVectorElementType() &&
7523-
"Insert subvector VTs must have the same element type!");
7524-
assert((VT.isScalableVector() || N2VT.isFixedLengthVector()) &&
7525-
"Cannot insert a scalable vector into a fixed length vector!");
7526-
}
7527-
if (VT.isRISCVVectorTuple())
7528-
assert((N2VT.isScalableVector() || N2VT.isRISCVVectorTuple()) &&
7529-
"Cannot insert a fixed length vector into a RISCV vector tuple!");
7519+
assert(VT.getVectorElementType() == N2VT.getVectorElementType() &&
7520+
"Insert subvector VTs must have the same element type!");
7521+
assert((VT.isScalableVector() || N2VT.isFixedLengthVector()) &&
7522+
"Cannot insert a scalable vector into a fixed length vector!");
75307523
assert((VT.isScalableVector() != N2VT.isScalableVector() ||
75317524
VT.getVectorMinNumElements() >= N2VT.getVectorMinNumElements()) &&
75327525
"Insert subvector must be from smaller vector to larger vector!");
75337526
assert(isa<ConstantSDNode>(N3) &&
75347527
"Insert subvector index must be constant");
75357528
assert((VT.isScalableVector() != N2VT.isScalableVector() ||
7536-
((VT.isRISCVVectorTuple() ? 0 : N2VT.getVectorMinNumElements()) +
7537-
N3->getAsZExtVal()) <= VT.getVectorMinNumElements()) &&
7529+
(N2VT.getVectorMinNumElements() + N3->getAsZExtVal()) <=
7530+
VT.getVectorMinNumElements()) &&
75387531
"Insert subvector overflow!");
75397532
assert(N3->getAsAPIntVal().getBitWidth() ==
75407533
TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() &&

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3055,7 +3055,7 @@ bool TargetLowering::SimplifyDemandedVectorElts(
30553055
return false;
30563056

30573057
// TODO: For now we assume we know nothing about scalable vectors.
3058-
if (VT.isScalableVector() || VT.isRISCVVectorTuple())
3058+
if (VT.isScalableVector())
30593059
return false;
30603060

30613061
assert(VT.getVectorNumElements() == NumElts &&

‎llvm/lib/CodeGen/TargetLoweringBase.cpp‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1382,10 +1382,6 @@ void TargetLoweringBase::computeRegisterProperties(
13821382
// Try to widen the vector.
13831383
for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
13841384
MVT SVT = (MVT::SimpleValueType) nVT;
1385-
// Skip RISCV vector tuple types since they don't involve in any
1386-
// widen/narrow operation.
1387-
if (SVT.isRISCVVectorTuple())
1388-
continue;
13891385
if (SVT.getVectorElementType() == EltVT &&
13901386
SVT.isScalableVector() == IsScalable &&
13911387
SVT.getVectorElementCount().getKnownMinValue() >

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1681,12 +1681,6 @@ MCRegister RISCVAsmParser::matchRegisterNameHelper(StringRef Name) const {
16811681
Reg = MatchRegisterAltName(Name);
16821682
if (isRVE() && Reg >= RISCV::X16 && Reg <= RISCV::X31)
16831683
Reg = RISCV::NoRegister;
1684-
1685-
// Replace vector tuple with the starting register, e.g. V4M4_V8M4 -> V4
1686-
for (int i = 30; i >= 0; --i)
1687-
if (Name.starts_with("V" + utostr(i)))
1688-
return RISCV::V0 + i;
1689-
16901684
return Reg;
16911685
}
16921686

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2147,7 +2147,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
21472147
}
21482148
break;
21492149
}
2150-
case ISD::INSERT_SUBVECTOR: {
2150+
case ISD::INSERT_SUBVECTOR:
2151+
case RISCVISD::INSERT_SUBVECTOR: {
21512152
SDValue V = Node->getOperand(0);
21522153
SDValue SubV = Node->getOperand(1);
21532154
SDLoc DL(SubV);
@@ -2214,7 +2215,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
22142215
ReplaceNode(Node, Insert.getNode());
22152216
return;
22162217
}
2217-
case ISD::EXTRACT_SUBVECTOR: {
2218+
case ISD::EXTRACT_SUBVECTOR:
2219+
case RISCVISD::EXTRACT_SUBVECTOR: {
22182220
SDValue V = Node->getOperand(0);
22192221
auto Idx = Node->getConstantOperandVal(1);
22202222
MVT InVT = V.getSimpleValueType();

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -2348,8 +2348,7 @@ bool RISCVTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
23482348
return false;
23492349

23502350
// Only support extracting a fixed from a fixed vector for now.
2351-
if (ResVT.isScalableVector() || SrcVT.isScalableVector() ||
2352-
SrcVT.isRISCVVectorTuple())
2351+
if (ResVT.isScalableVector() || SrcVT.isScalableVector())
23532352
return false;
23542353

23552354
EVT EltVT = ResVT.getVectorElementType();
@@ -2589,11 +2588,8 @@ unsigned RISCVTargetLowering::getSubregIndexByMVT(MVT VT, unsigned Index) {
25892588
}
25902589

25912590
unsigned RISCVTargetLowering::getRegClassIDForVecVT(MVT VT) {
2592-
if (VT.getVectorElementType() == MVT::i1)
2593-
return RISCV::VRRegClassID;
2594-
25952591
if (VT.isRISCVVectorTuple()) {
2596-
unsigned NF = VT.getVectorNumElements();
2592+
unsigned NF = VT.getRISCVVectorTupleNumFields();
25972593
unsigned RegsPerField = std::max(1U, (unsigned)VT.getSizeInBits() /
25982594
(NF * RISCV::RVVBitsPerBlock));
25992595
switch (RegsPerField) {
@@ -2630,6 +2626,8 @@ unsigned RISCVTargetLowering::getRegClassIDForVecVT(MVT VT) {
26302626
llvm_unreachable("Invalid vector tuple type RegClass.");
26312627
}
26322628

2629+
if (VT.getVectorElementType() == MVT::i1)
2630+
return RISCV::VRRegClassID;
26332631
return getRegClassIDForLMUL(getLMUL(VT));
26342632
}
26352633

@@ -2646,7 +2644,6 @@ RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(
26462644
RISCV::VRM4RegClassID > RISCV::VRM2RegClassID &&
26472645
RISCV::VRM2RegClassID > RISCV::VRRegClassID),
26482646
"Register classes not ordered");
2649-
26502647
unsigned VecRegClassID = getRegClassIDForVecVT(VecVT);
26512648
unsigned SubRegClassID = getRegClassIDForVecVT(SubVecVT);
26522649

@@ -7043,7 +7040,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
70437040
MachineFrameInfo &MFI = MF.getFrameInfo();
70447041
SDLoc DL(Op);
70457042
MVT XLenVT = Subtarget.getXLenVT();
7046-
unsigned NF = VecTy.getVectorMinNumElements();
7043+
unsigned NF = VecTy.getRISCVVectorTupleNumFields();
70477044
unsigned Sz = VecTy.getSizeInBits();
70487045
unsigned NumElts = Sz / (NF * 8);
70497046
int Log2LMUL = Log2_64(NumElts) - 3;
@@ -7064,7 +7061,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
70647061
SDValue LoadVal = DAG.getLoad(
70657062
MVT::getScalableVectorVT(MVT::i8, NumElts), DL, DAG.getEntryNode(),
70667063
BasePtr, Load->getPointerInfo(), Align(8));
7067-
Ret = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VecTy, Ret, LoadVal,
7064+
Ret = DAG.getNode(RISCVISD::INSERT_SUBVECTOR, DL, VecTy, Ret, LoadVal,
70687065
DAG.getVectorIdxConstant(i, DL));
70697066
BasePtr = DAG.getNode(ISD::ADD, DL, XLenVT, BasePtr, VROffset, Flag);
70707067
}
@@ -7087,7 +7084,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
70877084
MachineFrameInfo &MFI = MF.getFrameInfo();
70887085
SDLoc DL(Op);
70897086
MVT XLenVT = Subtarget.getXLenVT();
7090-
unsigned NF = VecTy.getVectorMinNumElements();
7087+
unsigned NF = VecTy.getRISCVVectorTupleNumFields();
70917088
unsigned Sz = VecTy.getSizeInBits();
70927089
unsigned NumElts = Sz / (NF * 8);
70937090
int Log2LMUL = Log2_64(NumElts) - 3;
@@ -7106,7 +7103,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
71067103

71077104
// Extract subregisters in a vector tuple and store them individually.
71087105
for (unsigned i = 0; i < NF; ++i) {
7109-
auto Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
7106+
auto Extract = DAG.getNode(RISCVISD::EXTRACT_SUBVECTOR, DL,
71107107
MVT::getScalableVectorVT(MVT::i8, NumElts),
71117108
StoredVal, DAG.getVectorIdxConstant(i, DL));
71127109
Ret = DAG.getStore(Chain, DL, Extract, BasePtr, Store->getPointerInfo(),
@@ -9297,14 +9294,14 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
92979294
SDValue SubVec = Op.getOperand(2);
92989295
SDValue Index = Op.getOperand(3);
92999296

9300-
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, Op.getValueType(), Vec,
9297+
return DAG.getNode(RISCVISD::INSERT_SUBVECTOR, DL, Op.getValueType(), Vec,
93019298
SubVec, Index);
93029299
}
93039300
case Intrinsic::riscv_vector_extract: {
93049301
SDValue Vec = Op.getOperand(1);
93059302
SDValue Index = Op.getOperand(2);
93069303

9307-
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, Op.getValueType(), Vec,
9304+
return DAG.getNode(RISCVISD::EXTRACT_SUBVECTOR, DL, Op.getValueType(), Vec,
93089305
Index);
93099306
}
93109307
case Intrinsic::thread_pointer: {
@@ -9744,7 +9741,7 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
97449741
SmallVector<SDValue, 9> Results;
97459742
for (unsigned int RetIdx = 0; RetIdx < NF; RetIdx++) {
97469743
SDValue SubVec =
9747-
DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ContainerVT,
9744+
DAG.getNode(RISCVISD::EXTRACT_SUBVECTOR, DL, ContainerVT,
97489745
Result.getValue(0), DAG.getVectorIdxConstant(RetIdx, DL));
97499746
Results.push_back(convertFromScalableVector(VT, SubVec, DAG, Subtarget));
97509747
}
@@ -9864,7 +9861,7 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
98649861
SDValue StoredVal = DAG.getUNDEF(VecTupTy);
98659862
for (unsigned i = 0; i < NF; i++)
98669863
StoredVal = DAG.getNode(
9867-
ISD::INSERT_SUBVECTOR, DL, VecTupTy, StoredVal,
9864+
RISCVISD::INSERT_SUBVECTOR, DL, VecTupTy, StoredVal,
98689865
convertToScalableVector(
98699866
ContainerVT, FixedIntrinsic->getOperand(2 + i), DAG, Subtarget),
98709867
DAG.getVectorIdxConstant(i, DL));
@@ -19504,7 +19501,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
1950419501
Reg = State.AllocateReg(ArgFPR32s);
1950519502
else if (ValVT == MVT::f64 && !UseGPRForF64)
1950619503
Reg = State.AllocateReg(ArgFPR64s);
19507-
else if (ValVT.isVector()) {
19504+
else if (ValVT.isVector() || ValVT.isRISCVVectorTuple()) {
1950819505
Reg = allocateRVVReg(ValVT, ValNo, FirstMaskArgument, State, TLI);
1950919506
if (!Reg) {
1951019507
// For return values, the vector must be passed fully via registers or
@@ -19555,7 +19552,8 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
1955519552
}
1955619553

1955719554
assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT ||
19558-
(TLI.getSubtarget().hasVInstructions() && ValVT.isVector())) &&
19555+
(TLI.getSubtarget().hasVInstructions() &&
19556+
(ValVT.isVector() || ValVT.isRISCVVectorTuple()))) &&
1955919557
"Expected an XLenVT or vector types at this stage");
1956019558

1956119559
if (Reg) {
@@ -20933,6 +20931,8 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
2093320931
NODE_NAME_CASE(CZERO_EQZ)
2093420932
NODE_NAME_CASE(CZERO_NEZ)
2093520933
NODE_NAME_CASE(SW_GUARDED_BRIND)
20934+
NODE_NAME_CASE(INSERT_SUBVECTOR)
20935+
NODE_NAME_CASE(EXTRACT_SUBVECTOR)
2093620936
NODE_NAME_CASE(SF_VC_XV_SE)
2093720937
NODE_NAME_CASE(SF_VC_IV_SE)
2093820938
NODE_NAME_CASE(SF_VC_VV_SE)
@@ -21867,17 +21867,17 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
2186721867
}
2186821868

2186921869
if (ValueVT.isRISCVVectorTuple() && PartVT.isRISCVVectorTuple()) {
21870-
unsigned ValNF = ValueVT.getVectorNumElements();
21871-
unsigned ValLMUL = std::max(1U, (unsigned)ValueVT.getSizeInBits() /
21872-
(ValNF * RISCV::RVVBitsPerBlock));
21873-
unsigned PartNF = PartVT.getVectorNumElements();
21874-
unsigned PartLMUL = std::max(1U, (unsigned)PartVT.getSizeInBits() /
21875-
(PartNF * RISCV::RVVBitsPerBlock));
21870+
unsigned ValNF = ValueVT.getRISCVVectorTupleNumFields();
21871+
unsigned ValLMUL =
21872+
divideCeil(ValueVT.getSizeInBits(), ValNF * RISCV::RVVBitsPerBlock);
21873+
unsigned PartNF = PartVT.getRISCVVectorTupleNumFields();
21874+
unsigned PartLMUL =
21875+
divideCeil(PartVT.getSizeInBits(), PartNF * RISCV::RVVBitsPerBlock);
2187621876
assert(ValNF == PartNF && ValLMUL == PartLMUL &&
21877-
"RISCV vector tuple type only accepts same register class type "
21877+
"RISC-V vector tuple type only accepts same register class type "
2187821878
"INSERT_SUBVECTOR");
2187921879

21880-
Val = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT),
21880+
Val = DAG.getNode(RISCVISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT),
2188121881
Val, DAG.getVectorIdxConstant(0, DL));
2188221882
Parts[0] = Val;
2188321883
return true;

‎llvm/lib/Target/RISCV/RISCVISelLowering.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -436,6 +436,9 @@ enum NodeType : unsigned {
436436
STRICT_FSETCCS_VL,
437437
STRICT_VFROUND_NOEXCEPT_VL,
438438
LAST_RISCV_STRICTFP_OPCODE = STRICT_VFROUND_NOEXCEPT_VL,
439+
440+
INSERT_SUBVECTOR,
441+
EXTRACT_SUBVECTOR,
439442

440443
SF_VC_XV_SE,
441444
SF_VC_IV_SE,

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