@@ -42,7 +42,7 @@ using namespace lld::elf;
4242
4343uint32_t OutputSection::getPhdrFlags () const {
4444 uint32_t ret = 0 ;
45- if (config-> emachine != EM_ARM || !(flags & SHF_ARM_PURECODE))
45+ if (ctx. arg . emachine != EM_ARM || !(flags & SHF_ARM_PURECODE))
4646 ret |= PF_R;
4747 if (flags & SHF_WRITE)
4848 ret |= PF_W;
@@ -82,7 +82,7 @@ static bool canMergeToProgbits(unsigned type) {
8282 return type == SHT_NOBITS || type == SHT_PROGBITS || type == SHT_INIT_ARRAY ||
8383 type == SHT_PREINIT_ARRAY || type == SHT_FINI_ARRAY ||
8484 type == SHT_NOTE ||
85- (type == SHT_X86_64_UNWIND && config-> emachine == EM_X86_64);
85+ (type == SHT_X86_64_UNWIND && ctx. arg . emachine == EM_X86_64);
8686}
8787
8888// Record that isec will be placed in the OutputSection. isec does not become
@@ -130,9 +130,9 @@ void OutputSection::commitSection(InputSection *isec) {
130130 if (type != SHT_NOBITS) {
131131 errorOrWarn (" section type mismatch for " + isec->name + " \n >>> " +
132132 toString (isec) + " : " +
133- getELFSectionTypeName (config-> emachine , isec->type ) +
133+ getELFSectionTypeName (ctx. arg . emachine , isec->type ) +
134134 " \n >>> output section " + name + " : " +
135- getELFSectionTypeName (config-> emachine , type));
135+ getELFSectionTypeName (ctx. arg . emachine , type));
136136 }
137137 }
138138 if (!typeIsSet)
@@ -155,7 +155,7 @@ void OutputSection::commitSection(InputSection *isec) {
155155
156156 isec->parent = this ;
157157 uint64_t andMask =
158- config-> emachine == EM_ARM ? (uint64_t )SHF_ARM_PURECODE : 0 ;
158+ ctx. arg . emachine == EM_ARM ? (uint64_t )SHF_ARM_PURECODE : 0 ;
159159 uint64_t orMask = ~andMask;
160160 uint64_t andFlags = (flags & isec->flags ) & andMask;
161161 uint64_t orFlags = (flags | isec->flags ) & orMask;
@@ -176,7 +176,7 @@ static MergeSyntheticSection *createMergeSynthetic(StringRef name,
176176 uint32_t type,
177177 uint64_t flags,
178178 uint32_t addralign) {
179- if ((flags & SHF_STRINGS) && config-> optimize >= 2 )
179+ if ((flags & SHF_STRINGS) && ctx. arg . optimize >= 2 )
180180 return make<MergeTailSection>(name, type, flags, addralign);
181181 return make<MergeNoTailSection>(name, type, flags, addralign);
182182}
@@ -261,7 +261,7 @@ static void sortByOrder(MutableArrayRef<InputSection *> in,
261261}
262262
263263uint64_t elf::getHeaderSize () {
264- if (config-> oFormatBinary )
264+ if (ctx. arg . oFormatBinary )
265265 return 0 ;
266266 return ctx.out .elfHeader ->size + ctx.out .programHeaders ->size ;
267267}
@@ -348,10 +348,10 @@ template <class ELFT> void OutputSection::maybeCompress() {
348348 DebugCompressionType ctype = DebugCompressionType::None;
349349 size_t compressedSize = sizeof (Elf_Chdr);
350350 unsigned level = 0 ; // default compression level
351- if (!(flags & SHF_ALLOC) && config-> compressDebugSections &&
351+ if (!(flags & SHF_ALLOC) && ctx. arg . compressDebugSections &&
352352 name.starts_with (" .debug_" ))
353- ctype = *config-> compressDebugSections ;
354- for (auto &[glob, t, l] : config-> compressSections )
353+ ctype = *ctx. arg . compressDebugSections ;
354+ for (auto &[glob, t, l] : ctx. arg . compressSections )
355355 if (glob.match (name))
356356 std::tie (ctype, level) = {t, l};
357357 if (ctype == DebugCompressionType::None)
@@ -529,7 +529,7 @@ void OutputSection::writeTo(uint8_t *buf, parallel::TaskGroup &tg) {
529529
530530 // When in Arm BE8 mode, the linker has to convert the big-endian
531531 // instructions to little-endian, leaving the data big-endian.
532- if (config-> emachine == EM_ARM && !config-> isLE && config-> armBe8 &&
532+ if (ctx. arg . emachine == EM_ARM && !ctx. arg . isLE && ctx. arg . armBe8 &&
533533 (flags & SHF_EXECINSTR))
534534 convertArmInstructionstoBE8 (isec, buf + isec->outSecOff );
535535
@@ -661,7 +661,7 @@ static size_t relToCrel(raw_svector_ostream &os, Elf_Crel<ELFT::Is64Bits> &out,
661661 for (auto rel : rels) {
662662 encodeOneCrel<typename ELFT::uint>(
663663 os, out, sec->getVA (rel.r_offset ), file.getRelocTargetSym (rel),
664- rel.getType (config-> isMips64EL ), getAddend<ELFT>(rel));
664+ rel.getType (ctx. arg . isMips64EL ), getAddend<ELFT>(rel));
665665 }
666666 return rels.size ();
667667}
@@ -690,10 +690,10 @@ template <bool is64> void OutputSection::finalizeNonAllocCrel() {
690690
691691 // Convert REL[A] to CREL.
692692 if constexpr (is64) {
693- totalCount += config-> isLE ? relToCrel<ELF64LE>(os, out, relSec, sec)
693+ totalCount += ctx. arg . isLE ? relToCrel<ELF64LE>(os, out, relSec, sec)
694694 : relToCrel<ELF64BE>(os, out, relSec, sec);
695695 } else {
696- totalCount += config-> isLE ? relToCrel<ELF32LE>(os, out, relSec, sec)
696+ totalCount += ctx. arg . isLE ? relToCrel<ELF32LE>(os, out, relSec, sec)
697697 : relToCrel<ELF32BE>(os, out, relSec, sec);
698698 }
699699 }
@@ -722,7 +722,7 @@ void OutputSection::finalize() {
722722 return ;
723723 }
724724
725- if (!config-> copyRelocs || !isStaticRelSecType (type))
725+ if (!ctx. arg . copyRelocs || !isStaticRelSecType (type))
726726 return ;
727727
728728 // Skip if 'first' is synthetic, i.e. not a section created by --emit-relocs.
@@ -740,7 +740,7 @@ void OutputSection::finalize() {
740740 flags |= SHF_INFO_LINK;
741741 // Finalize the content of non-alloc CREL.
742742 if (type == SHT_CREL) {
743- if (config-> is64 )
743+ if (ctx. arg . is64 )
744744 finalizeNonAllocCrel<true >();
745745 else
746746 finalizeNonAllocCrel<false >();
@@ -863,7 +863,7 @@ std::array<uint8_t, 4> OutputSection::getFiller() {
863863}
864864
865865void OutputSection::checkDynRelAddends (const uint8_t *bufStart) {
866- assert (config-> writeAddends && config-> checkDynamicRelocs );
866+ assert (ctx. arg . writeAddends && ctx. arg . checkDynamicRelocs );
867867 assert (isStaticRelSecType (type));
868868 SmallVector<InputSection *, 0 > storage;
869869 ArrayRef<InputSection *> sections = getInputSections (*this , storage);
@@ -881,7 +881,7 @@ void OutputSection::checkDynRelAddends(const uint8_t *bufStart) {
881881 assert (relOsec != nullptr && " missing output section for relocation" );
882882 // Some targets have NOBITS synthetic sections with dynamic relocations
883883 // with non-zero addends. Skip such sections.
884- if (is_contained ({EM_PPC, EM_PPC64}, config-> emachine ) &&
884+ if (is_contained ({EM_PPC, EM_PPC64}, ctx. arg . emachine ) &&
885885 (rel.inputSec == ctx.in .ppc64LongBranchTarget .get () ||
886886 rel.inputSec == ctx.in .igotPlt .get ()))
887887 continue ;
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