[AArch64] Addition gisel tests for udiv by constant and zext/sext/trunc. NFC

Author: davemgreen

llvm/test/CodeGen/AArch64/arm64-neon-mul-div-cte.ll

@@ -1,48 +1,153 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI:       warning: Instruction selection used fallback path for udiv_v2i64
 
 define <16 x i8> @div16xi8(<16 x i8> %x) {
-; CHECK-LABEL: div16xi8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    movi v1.16b, #41
-; CHECK-NEXT:    smull2 v2.8h, v0.16b, v1.16b
-; CHECK-NEXT:    smull v0.8h, v0.8b, v1.8b
-; CHECK-NEXT:    uzp2 v0.16b, v0.16b, v2.16b
-; CHECK-NEXT:    sshr v0.16b, v0.16b, #2
-; CHECK-NEXT:    usra v0.16b, v0.16b, #7
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: div16xi8:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    movi v1.16b, #41
+; CHECK-SD-NEXT:    smull2 v2.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT:    smull v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT:    uzp2 v0.16b, v0.16b, v2.16b
+; CHECK-SD-NEXT:    sshr v0.16b, v0.16b, #2
+; CHECK-SD-NEXT:    usra v0.16b, v0.16b, #7
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: div16xi8:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    smov w9, v0.b[0]
+; CHECK-GI-NEXT:    mov w8, #25 // =0x19
+; CHECK-GI-NEXT:    smov w10, v0.b[1]
+; CHECK-GI-NEXT:    smov w11, v0.b[2]
+; CHECK-GI-NEXT:    smov w12, v0.b[3]
+; CHECK-GI-NEXT:    smov w13, v0.b[4]
+; CHECK-GI-NEXT:    smov w14, v0.b[5]
+; CHECK-GI-NEXT:    smov w15, v0.b[6]
+; CHECK-GI-NEXT:    smov w16, v0.b[7]
+; CHECK-GI-NEXT:    smov w17, v0.b[8]
+; CHECK-GI-NEXT:    smov w18, v0.b[9]
+; CHECK-GI-NEXT:    sdiv w9, w9, w8
+; CHECK-GI-NEXT:    sdiv w10, w10, w8
+; CHECK-GI-NEXT:    fmov s1, w9
+; CHECK-GI-NEXT:    sdiv w11, w11, w8
+; CHECK-GI-NEXT:    mov v1.b[1], w10
+; CHECK-GI-NEXT:    smov w10, v0.b[10]
+; CHECK-GI-NEXT:    sdiv w12, w12, w8
+; CHECK-GI-NEXT:    mov v1.b[2], w11
+; CHECK-GI-NEXT:    smov w11, v0.b[11]
+; CHECK-GI-NEXT:    sdiv w13, w13, w8
+; CHECK-GI-NEXT:    mov v1.b[3], w12
+; CHECK-GI-NEXT:    smov w12, v0.b[12]
+; CHECK-GI-NEXT:    sdiv w14, w14, w8
+; CHECK-GI-NEXT:    mov v1.b[4], w13
+; CHECK-GI-NEXT:    smov w13, v0.b[13]
+; CHECK-GI-NEXT:    sdiv w15, w15, w8
+; CHECK-GI-NEXT:    mov v1.b[5], w14
+; CHECK-GI-NEXT:    sdiv w16, w16, w8
+; CHECK-GI-NEXT:    mov v1.b[6], w15
+; CHECK-GI-NEXT:    sdiv w17, w17, w8
+; CHECK-GI-NEXT:    mov v1.b[7], w16
+; CHECK-GI-NEXT:    sdiv w9, w18, w8
+; CHECK-GI-NEXT:    mov v1.b[8], w17
+; CHECK-GI-NEXT:    sdiv w10, w10, w8
+; CHECK-GI-NEXT:    mov v1.b[9], w9
+; CHECK-GI-NEXT:    smov w9, v0.b[14]
+; CHECK-GI-NEXT:    sdiv w11, w11, w8
+; CHECK-GI-NEXT:    mov v1.b[10], w10
+; CHECK-GI-NEXT:    smov w10, v0.b[15]
+; CHECK-GI-NEXT:    sdiv w12, w12, w8
+; CHECK-GI-NEXT:    mov v1.b[11], w11
+; CHECK-GI-NEXT:    sdiv w13, w13, w8
+; CHECK-GI-NEXT:    mov v1.b[12], w12
+; CHECK-GI-NEXT:    sdiv w9, w9, w8
+; CHECK-GI-NEXT:    mov v1.b[13], w13
+; CHECK-GI-NEXT:    sdiv w8, w10, w8
+; CHECK-GI-NEXT:    mov v1.b[14], w9
+; CHECK-GI-NEXT:    mov v1.b[15], w8
+; CHECK-GI-NEXT:    mov v0.16b, v1.16b
+; CHECK-GI-NEXT:    ret
   %div = sdiv <16 x i8> %x, <i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25>
   ret <16 x i8> %div
 }
 
 define <8 x i16> @div8xi16(<8 x i16> %x) {
-; CHECK-LABEL: div8xi16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #40815 // =0x9f6f
-; CHECK-NEXT:    dup v1.8h, w8
-; CHECK-NEXT:    smull2 v2.4s, v0.8h, v1.8h
-; CHECK-NEXT:    smull v1.4s, v0.4h, v1.4h
-; CHECK-NEXT:    uzp2 v1.8h, v1.8h, v2.8h
-; CHECK-NEXT:    add v0.8h, v1.8h, v0.8h
-; CHECK-NEXT:    sshr v0.8h, v0.8h, #12
-; CHECK-NEXT:    usra v0.8h, v0.8h, #15
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: div8xi16:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #40815 // =0x9f6f
+; CHECK-SD-NEXT:    dup v1.8h, w8
+; CHECK-SD-NEXT:    smull2 v2.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT:    smull v1.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT:    uzp2 v1.8h, v1.8h, v2.8h
+; CHECK-SD-NEXT:    add v0.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT:    sshr v0.8h, v0.8h, #12
+; CHECK-SD-NEXT:    usra v0.8h, v0.8h, #15
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: div8xi16:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    smov w9, v0.h[0]
+; CHECK-GI-NEXT:    mov w8, #6577 // =0x19b1
+; CHECK-GI-NEXT:    smov w10, v0.h[1]
+; CHECK-GI-NEXT:    smov w11, v0.h[2]
+; CHECK-GI-NEXT:    smov w12, v0.h[3]
+; CHECK-GI-NEXT:    smov w13, v0.h[4]
+; CHECK-GI-NEXT:    smov w14, v0.h[5]
+; CHECK-GI-NEXT:    sdiv w9, w9, w8
+; CHECK-GI-NEXT:    sdiv w10, w10, w8
+; CHECK-GI-NEXT:    fmov s1, w9
+; CHECK-GI-NEXT:    sdiv w11, w11, w8
+; CHECK-GI-NEXT:    mov v1.h[1], w10
+; CHECK-GI-NEXT:    smov w10, v0.h[6]
+; CHECK-GI-NEXT:    sdiv w12, w12, w8
+; CHECK-GI-NEXT:    mov v1.h[2], w11
+; CHECK-GI-NEXT:    smov w11, v0.h[7]
+; CHECK-GI-NEXT:    sdiv w13, w13, w8
+; CHECK-GI-NEXT:    mov v1.h[3], w12
+; CHECK-GI-NEXT:    sdiv w9, w14, w8
+; CHECK-GI-NEXT:    mov v1.h[4], w13
+; CHECK-GI-NEXT:    sdiv w10, w10, w8
+; CHECK-GI-NEXT:    mov v1.h[5], w9
+; CHECK-GI-NEXT:    sdiv w8, w11, w8
+; CHECK-GI-NEXT:    mov v1.h[6], w10
+; CHECK-GI-NEXT:    mov v1.h[7], w8
+; CHECK-GI-NEXT:    mov v0.16b, v1.16b
+; CHECK-GI-NEXT:    ret
   %div = sdiv <8 x i16> %x, <i16 6577, i16 6577, i16 6577, i16 6577, i16 6577, i16 6577, i16 6577, i16 6577>
   ret <8 x i16> %div
 }
 
 define <4 x i32> @div32xi4(<4 x i32> %x) {
-; CHECK-LABEL: div32xi4:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #7527 // =0x1d67
-; CHECK-NEXT:    movk w8, #28805, lsl #16
-; CHECK-NEXT:    dup v1.4s, w8
-; CHECK-NEXT:    smull2 v2.2d, v0.4s, v1.4s
-; CHECK-NEXT:    smull v0.2d, v0.2s, v1.2s
-; CHECK-NEXT:    uzp2 v1.4s, v0.4s, v2.4s
-; CHECK-NEXT:    sshr v0.4s, v1.4s, #22
-; CHECK-NEXT:    usra v0.4s, v1.4s, #31
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: div32xi4:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #7527 // =0x1d67
+; CHECK-SD-NEXT:    movk w8, #28805, lsl #16
+; CHECK-SD-NEXT:    dup v1.4s, w8
+; CHECK-SD-NEXT:    smull2 v2.2d, v0.4s, v1.4s
+; CHECK-SD-NEXT:    smull v0.2d, v0.2s, v1.2s
+; CHECK-SD-NEXT:    uzp2 v1.4s, v0.4s, v2.4s
+; CHECK-SD-NEXT:    sshr v0.4s, v1.4s, #22
+; CHECK-SD-NEXT:    usra v0.4s, v1.4s, #31
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: div32xi4:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    fmov w9, s0
+; CHECK-GI-NEXT:    mov w8, #39957 // =0x9c15
+; CHECK-GI-NEXT:    mov w10, v0.s[1]
+; CHECK-GI-NEXT:    movk w8, #145, lsl #16
+; CHECK-GI-NEXT:    mov w11, v0.s[2]
+; CHECK-GI-NEXT:    mov w12, v0.s[3]
+; CHECK-GI-NEXT:    sdiv w9, w9, w8
+; CHECK-GI-NEXT:    sdiv w10, w10, w8
+; CHECK-GI-NEXT:    mov v0.s[0], w9
+; CHECK-GI-NEXT:    sdiv w11, w11, w8
+; CHECK-GI-NEXT:    mov v0.s[1], w10
+; CHECK-GI-NEXT:    sdiv w8, w12, w8
+; CHECK-GI-NEXT:    mov v0.s[2], w11
+; CHECK-GI-NEXT:    mov v0.s[3], w8
+; CHECK-GI-NEXT:    ret
   %div = sdiv <4 x i32> %x, <i32 9542677, i32 9542677, i32 9542677, i32 9542677>
   ret <4 x i32> %div
 }
@@ -61,32 +166,78 @@ define <16 x i8> @udiv16xi8(<16 x i8> %x) {
 }
 
 define <8 x i16> @udiv8xi16(<8 x i16> %x) {
-; CHECK-LABEL: udiv8xi16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #16593 // =0x40d1
-; CHECK-NEXT:    dup v1.8h, w8
-; CHECK-NEXT:    umull2 v2.4s, v0.8h, v1.8h
-; CHECK-NEXT:    umull v1.4s, v0.4h, v1.4h
-; CHECK-NEXT:    uzp2 v1.8h, v1.8h, v2.8h
-; CHECK-NEXT:    sub v0.8h, v0.8h, v1.8h
-; CHECK-NEXT:    usra v1.8h, v0.8h, #1
-; CHECK-NEXT:    ushr v0.8h, v1.8h, #12
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: udiv8xi16:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #16593 // =0x40d1
+; CHECK-SD-NEXT:    dup v1.8h, w8
+; CHECK-SD-NEXT:    umull2 v2.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT:    umull v1.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT:    uzp2 v1.8h, v1.8h, v2.8h
+; CHECK-SD-NEXT:    sub v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT:    usra v1.8h, v0.8h, #1
+; CHECK-SD-NEXT:    ushr v0.8h, v1.8h, #12
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: udiv8xi16:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI4_0
+; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI4_0]
+; CHECK-GI-NEXT:    umull2 v2.4s, v0.8h, v1.8h
+; CHECK-GI-NEXT:    umull v1.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT:    uzp2 v1.8h, v1.8h, v2.8h
+; CHECK-GI-NEXT:    sub v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT:    usra v1.8h, v0.8h, #1
+; CHECK-GI-NEXT:    ushr v0.8h, v1.8h, #12
+; CHECK-GI-NEXT:    ret
   %div = udiv <8 x i16> %x, <i16 6537, i16 6537, i16 6537, i16 6537, i16 6537, i16 6537, i16 6537, i16 6537>
   ret <8 x i16> %div
 }
 
 define <4 x i32> @udiv32xi4(<4 x i32> %x) {
-; CHECK-LABEL: udiv32xi4:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #16747 // =0x416b
-; CHECK-NEXT:    movk w8, #31439, lsl #16
-; CHECK-NEXT:    dup v1.4s, w8
-; CHECK-NEXT:    umull2 v2.2d, v0.4s, v1.4s
-; CHECK-NEXT:    umull v0.2d, v0.2s, v1.2s
-; CHECK-NEXT:    uzp2 v0.4s, v0.4s, v2.4s
-; CHECK-NEXT:    ushr v0.4s, v0.4s, #22
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: udiv32xi4:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #16747 // =0x416b
+; CHECK-SD-NEXT:    movk w8, #31439, lsl #16
+; CHECK-SD-NEXT:    dup v1.4s, w8
+; CHECK-SD-NEXT:    umull2 v2.2d, v0.4s, v1.4s
+; CHECK-SD-NEXT:    umull v0.2d, v0.2s, v1.2s
+; CHECK-SD-NEXT:    uzp2 v0.4s, v0.4s, v2.4s
+; CHECK-SD-NEXT:    ushr v0.4s, v0.4s, #22
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: udiv32xi4:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI5_0
+; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI5_0]
+; CHECK-GI-NEXT:    umull2 v2.2d, v0.4s, v1.4s
+; CHECK-GI-NEXT:    umull v0.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT:    uzp2 v0.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT:    ushr v0.4s, v0.4s, #22
+; CHECK-GI-NEXT:    ret
   %div = udiv <4 x i32> %x, <i32 8743143, i32 8743143, i32 8743143, i32 8743143>
   ret <4 x i32> %div
 }
+
+define <2 x i64> @udiv_v2i64(<2 x i64> %a) {
+; CHECK-LABEL: udiv_v2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #9363 // =0x2493
+; CHECK-NEXT:    fmov x10, d0
+; CHECK-NEXT:    mov x9, v0.d[1]
+; CHECK-NEXT:    movk x8, #37449, lsl #16
+; CHECK-NEXT:    movk x8, #18724, lsl #32
+; CHECK-NEXT:    movk x8, #9362, lsl #48
+; CHECK-NEXT:    umulh x11, x10, x8
+; CHECK-NEXT:    umulh x8, x9, x8
+; CHECK-NEXT:    sub x10, x10, x11
+; CHECK-NEXT:    add x10, x11, x10, lsr #1
+; CHECK-NEXT:    sub x9, x9, x8
+; CHECK-NEXT:    add x8, x8, x9, lsr #1
+; CHECK-NEXT:    lsr x9, x10, #2
+; CHECK-NEXT:    fmov d0, x9
+; CHECK-NEXT:    lsr x8, x8, #2
+; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    ret
+  %r = udiv <2 x i64> %a, splat (i64 7)
+  ret <2 x i64> %r
+}

llvm/test/CodeGen/AArch64/arm64-vabs.ll

@@ -2,6 +2,8 @@
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck -check-prefixes=CHECK,CHECK-SD %s
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
+; CHECK-GI:       warning: Instruction selection used fallback path for uabd_i64
+
 define <8 x i16> @sabdl8h(ptr %A, ptr %B) nounwind {
 ; CHECK-LABEL: sabdl8h:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/sext.ll

@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI:       warning: Instruction selection used fallback path for sext_v2i64_v2i128
 
 define i16 @sext_i8_to_i16(i8 %a) {
 ; CHECK-LABEL: sext_i8_to_i16:
@@ -1241,3 +1243,18 @@ entry:
   %c = sext <16 x i10> %a to <16 x i64>
   ret <16 x i64> %c
 }
+
+define <2 x i128> @sext_v2i64_v2i128(<2 x i64> %a) {
+; CHECK-LABEL: sext_v2i64_v2i128:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    mov x8, v0.d[1]
+; CHECK-NEXT:    dup v1.2d, v0.d[1]
+; CHECK-NEXT:    fmov x0, d0
+; CHECK-NEXT:    fmov x2, d1
+; CHECK-NEXT:    asr x1, x0, #63
+; CHECK-NEXT:    asr x3, x8, #63
+; CHECK-NEXT:    ret
+entry:
+  %c = sext <2 x i64> %a to <2 x i128>
+  ret <2 x i128> %c
+}