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[RISCV] Add scheduling information for SiFive VCIX (#86093)
This adds `RISCVScheduleXSf.td` with `SchedWrite` definitions for all VCIX instructions and uses it in `RISCVSchedSiFive7.td` to set default latencies for these instructions, helping with issue #83391. Of course these default latencies cannot be accurate (since each coprocessor will have different latencies), but this seems to be enough to avoid some of the problematic behavior described in the bug. In any case, this seems to be enough to help with #83391 in our internal testing. A subsequent discussion is how to structure the code such that it's easier for downstream consumers of this to use `SiFive7` scheduling model with accurate VCIX latencies. But we can probably have a separate issue to discuss that.
1 parent 17d6bf0 commit 6da1966

9 files changed

+149
-12
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

Lines changed: 36 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -307,44 +307,68 @@ multiclass VPseudoVC_X<LMULInfo m, DAGOperand RS1Class,
307307
Operand OpClass = payload2> {
308308
let VLMul = m.value in {
309309
let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in {
310-
def "PseudoVC_" # NAME # "_SE_" # m.MX : VPseudoVC_X<OpClass, RS1Class>;
311-
def "PseudoVC_V_" # NAME # "_SE_" # m.MX : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>;
310+
def "PseudoVC_" # NAME # "_SE_" # m.MX
311+
: VPseudoVC_X<OpClass, RS1Class>,
312+
Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
313+
def "PseudoVC_V_" # NAME # "_SE_" # m.MX
314+
: VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>,
315+
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
312316
}
313-
def "PseudoVC_V_" # NAME # "_" # m.MX : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>;
317+
def "PseudoVC_V_" # NAME # "_" # m.MX
318+
: VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>,
319+
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
314320
}
315321
}
316322

317323
multiclass VPseudoVC_XV<LMULInfo m, DAGOperand RS1Class,
318324
Operand OpClass = payload2> {
319325
let VLMul = m.value in {
320326
let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in {
321-
def "PseudoVC_" # NAME # "_SE_" # m.MX : VPseudoVC_XV<OpClass, m.vrclass, RS1Class>;
322-
def "PseudoVC_V_" # NAME # "_SE_" # m.MX : VPseudoVC_V_XV<OpClass, m.vrclass, m.vrclass, RS1Class>;
327+
def "PseudoVC_" # NAME # "_SE_" # m.MX
328+
: VPseudoVC_XV<OpClass, m.vrclass, RS1Class>,
329+
Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
330+
def "PseudoVC_V_" # NAME # "_SE_" # m.MX
331+
: VPseudoVC_V_XV<OpClass, m.vrclass, m.vrclass, RS1Class>,
332+
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
323333
}
324-
def "PseudoVC_V_" # NAME # "_" # m.MX : VPseudoVC_V_XV<OpClass, m.vrclass, m.vrclass, RS1Class>;
334+
def "PseudoVC_V_" # NAME # "_" # m.MX
335+
: VPseudoVC_V_XV<OpClass, m.vrclass, m.vrclass, RS1Class>,
336+
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
325337
}
326338
}
327339

328340
multiclass VPseudoVC_XVV<LMULInfo m, DAGOperand RS1Class,
329341
Operand OpClass = payload2> {
330342
let VLMul = m.value in {
331343
let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in {
332-
def "PseudoVC_" # NAME # "_SE_" # m.MX : VPseudoVC_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>;
333-
def "PseudoVC_V_" # NAME # "_SE_" # m.MX : VPseudoVC_V_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>;
344+
def "PseudoVC_" # NAME # "_SE_" # m.MX
345+
: VPseudoVC_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>,
346+
Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
347+
def "PseudoVC_V_" # NAME # "_SE_" # m.MX
348+
: VPseudoVC_V_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>,
349+
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
334350
}
335-
def "PseudoVC_V_" # NAME # "_" # m.MX : VPseudoVC_V_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>;
351+
def "PseudoVC_V_" # NAME # "_" # m.MX
352+
: VPseudoVC_V_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>,
353+
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
336354
}
337355
}
338356

339357
multiclass VPseudoVC_XVW<LMULInfo m, DAGOperand RS1Class,
340358
Operand OpClass = payload2> {
341359
let VLMul = m.value in {
342360
let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in
343-
def "PseudoVC_" # NAME # "_SE_" # m.MX : VPseudoVC_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>;
361+
def "PseudoVC_" # NAME # "_SE_" # m.MX
362+
: VPseudoVC_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>,
363+
Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
344364
let Constraints = "@earlyclobber $rd, $rd = $rs3" in {
345365
let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in
346-
def "PseudoVC_V_" # NAME # "_SE_" # m.MX : VPseudoVC_V_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>;
347-
def "PseudoVC_V_" # NAME # "_" # m.MX : VPseudoVC_V_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>;
366+
def "PseudoVC_V_" # NAME # "_SE_" # m.MX
367+
: VPseudoVC_V_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>,
368+
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
369+
def "PseudoVC_V_" # NAME # "_" # m.MX
370+
: VPseudoVC_V_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>,
371+
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
348372
}
349373
}
350374
}

‎llvm/lib/Target/RISCV/RISCVSchedRocket.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -261,4 +261,5 @@ defm : UnsupportedSchedZbkx;
261261
defm : UnsupportedSchedZfa;
262262
defm : UnsupportedSchedZfh;
263263
defm : UnsupportedSchedSFB;
264+
defm : UnsupportedSchedXsfvcp;
264265
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -962,6 +962,54 @@ let Latency = 3 in
962962

963963
def : InstRW<[WriteIALU], (instrs COPY)>;
964964

965+
// VCIX
966+
//
967+
// In principle we don't know the latency of any VCIX instructions. But instead
968+
// of taking the default of 1, which can lead to issues [1], we assume that they
969+
// have a fairly high latency.
970+
//
971+
// [1] https://github.com/llvm/llvm-project/issues/83391
972+
foreach mx = SchedMxList in {
973+
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
974+
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
975+
let Latency = !mul(Cycles, 10),
976+
AcquireAtCycles = [0, 1],
977+
ReleaseAtCycles = [1, !add(1, Cycles)] in {
978+
defm "" : LMULWriteResMX<"WriteVC_V_I", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
979+
defm "" : LMULWriteResMX<"WriteVC_V_X", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
980+
defm "" : LMULWriteResMX<"WriteVC_V_IV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
981+
defm "" : LMULWriteResMX<"WriteVC_V_VV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
982+
defm "" : LMULWriteResMX<"WriteVC_V_XV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
983+
defm "" : LMULWriteResMX<"WriteVC_V_IVV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
984+
defm "" : LMULWriteResMX<"WriteVC_V_IVW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
985+
defm "" : LMULWriteResMX<"WriteVC_V_VVV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
986+
defm "" : LMULWriteResMX<"WriteVC_V_VVW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
987+
defm "" : LMULWriteResMX<"WriteVC_V_XVV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
988+
defm "" : LMULWriteResMX<"WriteVC_V_XVW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
989+
foreach f = ["FPR16", "FPR32", "FPR64"] in {
990+
defm "" : LMULWriteResMX<"WriteVC_V_" # f # "V", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
991+
defm "" : LMULWriteResMX<"WriteVC_V_" # f # "VV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
992+
defm "" : LMULWriteResMX<"WriteVC_V_" # f # "VW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
993+
}
994+
defm "" : LMULWriteResMX<"WriteVC_I", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
995+
defm "" : LMULWriteResMX<"WriteVC_X", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
996+
defm "" : LMULWriteResMX<"WriteVC_IV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
997+
defm "" : LMULWriteResMX<"WriteVC_VV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
998+
defm "" : LMULWriteResMX<"WriteVC_XV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
999+
defm "" : LMULWriteResMX<"WriteVC_IVV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1000+
defm "" : LMULWriteResMX<"WriteVC_IVW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1001+
defm "" : LMULWriteResMX<"WriteVC_VVV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1002+
defm "" : LMULWriteResMX<"WriteVC_VVW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1003+
defm "" : LMULWriteResMX<"WriteVC_XVV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1004+
defm "" : LMULWriteResMX<"WriteVC_XVW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1005+
foreach f = ["FPR16", "FPR32", "FPR64"] in {
1006+
defm "" : LMULWriteResMX<"WriteVC_" # f # "V", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1007+
defm "" : LMULWriteResMX<"WriteVC_" # f # "VV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1008+
defm "" : LMULWriteResMX<"WriteVC_" # f # "VW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1009+
}
1010+
}
1011+
}
1012+
9651013
//===----------------------------------------------------------------------===//
9661014

9671015
// Bypass and advance

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -366,4 +366,5 @@ defm : UnsupportedSchedZbkx;
366366
defm : UnsupportedSchedSFB;
367367
defm : UnsupportedSchedZfa;
368368
defm : UnsupportedSchedV;
369+
defm : UnsupportedSchedXsfvcp;
369370
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1040,4 +1040,5 @@ defm : UnsupportedSchedZbkb;
10401040
defm : UnsupportedSchedZbkx;
10411041
defm : UnsupportedSchedSFB;
10421042
defm : UnsupportedSchedZfa;
1043+
defm : UnsupportedSchedXsfvcp;
10431044
}

‎llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -212,4 +212,5 @@ defm : UnsupportedSchedZbkb;
212212
defm : UnsupportedSchedZbkx;
213213
defm : UnsupportedSchedZfa;
214214
defm : UnsupportedSchedZfh;
215+
defm : UnsupportedSchedXsfvcp;
215216
}

‎llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -311,4 +311,5 @@ defm : UnsupportedSchedZfa;
311311
defm : UnsupportedSchedZfh;
312312
defm : UnsupportedSchedSFB;
313313
defm : UnsupportedSchedZabha;
314+
defm : UnsupportedSchedXsfvcp;
314315
}

‎llvm/lib/Target/RISCV/RISCVSchedule.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -296,3 +296,4 @@ def : ReadAdvance<ReadAtomicHD, 0>;
296296
// Include the scheduler resources for other instruction extensions.
297297
include "RISCVScheduleZb.td"
298298
include "RISCVScheduleV.td"
299+
include "RISCVScheduleXSf.td"

‎llvm/lib/Target/RISCV/RISCVScheduleXSf.td

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
//===-- RISCVScheduleXSf.td - Scheduling Definitions XSf ---*- tablegen -*-===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
//
9+
// This file describes the scheduling information for SiFive extensions.
10+
//
11+
//===----------------------------------------------------------------------===//
12+
13+
multiclass LMULSchedWritesVCIX<string id>{
14+
defm "" : LMULSchedWrites<"WriteVC_" # id>;
15+
defm "" : LMULSchedWrites<"WriteVC_V_" # id>;
16+
}
17+
18+
defm "" : LMULSchedWritesVCIX<"I">;
19+
defm "" : LMULSchedWritesVCIX<"X">;
20+
defm "" : LMULSchedWritesVCIX<"IV">;
21+
defm "" : LMULSchedWritesVCIX<"VV">;
22+
defm "" : LMULSchedWritesVCIX<"XV">;
23+
defm "" : LMULSchedWritesVCIX<"IVV">;
24+
defm "" : LMULSchedWritesVCIX<"IVW">;
25+
defm "" : LMULSchedWritesVCIX<"VVV">;
26+
defm "" : LMULSchedWritesVCIX<"VVW">;
27+
defm "" : LMULSchedWritesVCIX<"XVV">;
28+
defm "" : LMULSchedWritesVCIX<"XVW">;
29+
foreach f = ["FPR16", "FPR32", "FPR64"] in {
30+
defm "" : LMULSchedWritesVCIX<f # "V">;
31+
defm "" : LMULSchedWritesVCIX<f # "VV">;
32+
defm "" : LMULSchedWritesVCIX<f # "VW">;
33+
}
34+
35+
multiclass LMULWriteResVCIX<string id, list<ProcResourceKind> resources>{
36+
defm : LMULWriteRes<"WriteVC_" # id, resources>;
37+
defm : LMULWriteRes<"WriteVC_V_" # id, resources>;
38+
}
39+
40+
multiclass UnsupportedSchedXsfvcp {
41+
let Unsupported = true in {
42+
defm : LMULWriteResVCIX<"I", []>;
43+
defm : LMULWriteResVCIX<"X", []>;
44+
defm : LMULWriteResVCIX<"IV", []>;
45+
defm : LMULWriteResVCIX<"VV", []>;
46+
defm : LMULWriteResVCIX<"XV", []>;
47+
defm : LMULWriteResVCIX<"IVV", []>;
48+
defm : LMULWriteResVCIX<"IVW", []>;
49+
defm : LMULWriteResVCIX<"VVV", []>;
50+
defm : LMULWriteResVCIX<"VVW", []>;
51+
defm : LMULWriteResVCIX<"XVV", []>;
52+
defm : LMULWriteResVCIX<"XVW", []>;
53+
foreach f = ["FPR16", "FPR32", "FPR64"] in {
54+
defm : LMULWriteResVCIX<f # "V", []>;
55+
defm : LMULWriteResVCIX<f # "VV", []>;
56+
defm : LMULWriteResVCIX<f # "VW", []>;
57+
}
58+
}
59+
}

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