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arsenmarsenm
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X86: Stop overriding getRegClass
This function should not be virtual; making this virtual was an AMDGPU hack that should be removed not spread to other backends. This does not need to be overridden to reserve registers. The register reservation mechanism is orthogonal to to the register class constraints of the instruction, this should be reporting the underlying instruction constraint. The registers are separately reserved, so they will be removed from the allocation order anyway. If the actual class needs to change based on the subtarget, it should probably generalize the LookupPtrRegClass mechanism. This was added by #70958. The new tests there for the class are probably not useful anymore. These instead should compile to the end and try to stress the allocation behavior.
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+16
-39
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6 files changed

+16
-39
lines changed

‎llvm/lib/Target/X86/X86InstrInfo.cpp‎

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -93,22 +93,6 @@ X86InstrInfo::X86InstrInfo(const X86Subtarget &STI)
9393
X86::CATCHRET, (STI.is64Bit() ? X86::RET64 : X86::RET32)),
9494
Subtarget(STI), RI(STI.getTargetTriple()) {}
9595

96-
const TargetRegisterClass *
97-
X86InstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
98-
const TargetRegisterInfo *TRI) const {
99-
auto *RC = TargetInstrInfo::getRegClass(MCID, OpNum, TRI);
100-
// If the target does not have egpr, then r16-r31 will be resereved for all
101-
// instructions.
102-
if (!RC || !Subtarget.hasEGPR())
103-
return RC;
104-
105-
if (X86II::canUseApxExtendedReg(MCID))
106-
return RC;
107-
108-
const X86RegisterInfo *RI = Subtarget.getRegisterInfo();
109-
return RI->constrainRegClassToNonRex2(RC);
110-
}
111-
11296
bool X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
11397
Register &SrcReg, Register &DstReg,
11498
unsigned &SubIdx) const {

‎llvm/lib/Target/X86/X86InstrInfo.h‎

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -240,16 +240,6 @@ class X86InstrInfo final : public X86GenInstrInfo {
240240
public:
241241
explicit X86InstrInfo(const X86Subtarget &STI);
242242

243-
/// Given a machine instruction descriptor, returns the register
244-
/// class constraint for OpNum, or NULL. Returned register class
245-
/// may be different from the definition in the TD file, e.g.
246-
/// GR*RegClass (definition in TD file)
247-
/// ->
248-
/// GR*_NOREX2RegClass (Returned register class)
249-
const TargetRegisterClass *
250-
getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
251-
const TargetRegisterInfo *TRI) const override;
252-
253243
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
254244
/// such, whenever a client has an instance of instruction info, it should
255245
/// always be able to get register info as well (through this method).

‎llvm/test/CodeGen/X86/apx/no-rex2-general.ll‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@ define i32 @map0(ptr nocapture noundef readonly %a, i64 noundef %b) {
1414
; SSE-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 4, [[COPY]], 0, $noreg :: (load (s32) from %ir.add.ptr)
1515
; SSE-NEXT: $eax = COPY [[MOV32rm]]
1616
; SSE-NEXT: RET 0, $eax
17+
;
1718
; AVX-LABEL: name: map0
1819
; AVX: bb.0.entry:
1920
; AVX-NEXT: liveins: $rdi, $rsi
@@ -38,12 +39,13 @@ define i32 @map1_or_vex(<2 x double> noundef %a) {
3839
; SSE-NEXT: [[CVTSD2SIrr_Int:%[0-9]+]]:gr32 = nofpexcept CVTSD2SIrr_Int [[COPY]], implicit $mxcsr
3940
; SSE-NEXT: $eax = COPY [[CVTSD2SIrr_Int]]
4041
; SSE-NEXT: RET 0, $eax
42+
;
4143
; AVX-LABEL: name: map1_or_vex
4244
; AVX: bb.0.entry:
4345
; AVX-NEXT: liveins: $xmm0
4446
; AVX-NEXT: {{ $}}
4547
; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
46-
; AVX-NEXT: [[VCVTSD2SIrr_Int:%[0-9]+]]:gr32_norex2 = nofpexcept VCVTSD2SIrr_Int [[COPY]], implicit $mxcsr
48+
; AVX-NEXT: [[VCVTSD2SIrr_Int:%[0-9]+]]:gr32 = nofpexcept VCVTSD2SIrr_Int [[COPY]], implicit $mxcsr
4749
; AVX-NEXT: $eax = COPY [[VCVTSD2SIrr_Int]]
4850
; AVX-NEXT: RET 0, $eax
4951
entry:
@@ -56,17 +58,18 @@ define <2 x i64> @map2_or_vex(ptr nocapture noundef readonly %b, i64 noundef %c)
5658
; SSE: bb.0.entry:
5759
; SSE-NEXT: liveins: $rdi, $rsi
5860
; SSE-NEXT: {{ $}}
59-
; SSE-NEXT: [[COPY:%[0-9]+]]:gr64_norex2_nosp = COPY $rsi
60-
; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64_norex2 = COPY $rdi
61+
; SSE-NEXT: [[COPY:%[0-9]+]]:gr64_nosp = COPY $rsi
62+
; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
6163
; SSE-NEXT: [[PABSBrm:%[0-9]+]]:vr128 = PABSBrm [[COPY1]], 4, [[COPY]], 0, $noreg :: (load (s128) from %ir.add.ptr)
6264
; SSE-NEXT: $xmm0 = COPY [[PABSBrm]]
6365
; SSE-NEXT: RET 0, $xmm0
66+
;
6467
; AVX-LABEL: name: map2_or_vex
6568
; AVX: bb.0.entry:
6669
; AVX-NEXT: liveins: $rdi, $rsi
6770
; AVX-NEXT: {{ $}}
68-
; AVX-NEXT: [[COPY:%[0-9]+]]:gr64_norex2_nosp = COPY $rsi
69-
; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64_norex2 = COPY $rdi
71+
; AVX-NEXT: [[COPY:%[0-9]+]]:gr64_nosp = COPY $rsi
72+
; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
7073
; AVX-NEXT: [[VPABSBrm:%[0-9]+]]:vr128 = VPABSBrm [[COPY1]], 4, [[COPY]], 0, $noreg :: (load (s128) from %ir.add.ptr)
7174
; AVX-NEXT: $xmm0 = COPY [[VPABSBrm]]
7275
; AVX-NEXT: RET 0, $xmm0

‎llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@ define dso_local void @amx(ptr noundef %data) {
77
; CHECK: bb.0.entry:
88
; CHECK-NEXT: liveins: $rdi
99
; CHECK-NEXT: {{ $}}
10-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64_norex2 = COPY $rdi
11-
; CHECK-NEXT: [[MOV32ri64_:%[0-9]+]]:gr64_norex2_nosp = MOV32ri64 8
10+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
11+
; CHECK-NEXT: [[MOV32ri64_:%[0-9]+]]:gr64_nosp = MOV32ri64 8
1212
; CHECK-NEXT: PTILELOADD 4, [[COPY]], 1, killed [[MOV32ri64_]], 0, $noreg
1313
; CHECK-NEXT: RET 0
1414
entry:

‎llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@ define void @x87(ptr %0, ptr %1) {
77
; CHECK: bb.0 (%ir-block.2):
88
; CHECK-NEXT: liveins: $rdi, $rsi
99
; CHECK-NEXT: {{ $}}
10-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64_norex2 = COPY $rsi
11-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64_norex2 = COPY $rdi
10+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
11+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
1212
; CHECK-NEXT: [[LD_Fp32m:%[0-9]+]]:rfp32 = nofpexcept LD_Fp32m [[COPY1]], 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %ir.0)
1313
; CHECK-NEXT: nofpexcept ST_Fp32m [[COPY]], 1, $noreg, 0, $noreg, killed [[LD_Fp32m]], implicit-def dead $fpsw, implicit $fpcw :: (store (s32) into %ir.1)
1414
; CHECK-NEXT: RET 0

‎llvm/test/CodeGen/X86/apx/no-rex2-special.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ define void @test_xsave(ptr %ptr, i32 %hi, i32 %lo) {
99
; CHECK-NEXT: {{ $}}
1010
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
1111
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
12-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64_norex2 = COPY $rdi
12+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
1313
; CHECK-NEXT: $edx = COPY [[COPY1]]
1414
; CHECK-NEXT: $eax = COPY [[COPY]]
1515
; CHECK-NEXT: XSAVE [[COPY2]], 1, $noreg, 0, $noreg, implicit $edx, implicit $eax
@@ -26,7 +26,7 @@ define void @test_xsave64(ptr %ptr, i32 %hi, i32 %lo) {
2626
; CHECK-NEXT: {{ $}}
2727
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
2828
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
29-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64_norex2 = COPY $rdi
29+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
3030
; CHECK-NEXT: $edx = COPY [[COPY1]]
3131
; CHECK-NEXT: $eax = COPY [[COPY]]
3232
; CHECK-NEXT: XSAVE64 [[COPY2]], 1, $noreg, 0, $noreg, implicit $edx, implicit $eax
@@ -43,7 +43,7 @@ define void @test_xrstor(ptr %ptr, i32 %hi, i32 %lo) {
4343
; CHECK-NEXT: {{ $}}
4444
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
4545
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
46-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64_norex2 = COPY $rdi
46+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
4747
; CHECK-NEXT: $edx = COPY [[COPY1]]
4848
; CHECK-NEXT: $eax = COPY [[COPY]]
4949
; CHECK-NEXT: XRSTOR [[COPY2]], 1, $noreg, 0, $noreg, implicit $edx, implicit $eax
@@ -60,7 +60,7 @@ define void @test_xrstor64(ptr %ptr, i32 %hi, i32 %lo) {
6060
; CHECK-NEXT: {{ $}}
6161
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
6262
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
63-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64_norex2 = COPY $rdi
63+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
6464
; CHECK-NEXT: $edx = COPY [[COPY1]]
6565
; CHECK-NEXT: $eax = COPY [[COPY]]
6666
; CHECK-NEXT: XRSTOR64 [[COPY2]], 1, $noreg, 0, $noreg, implicit $edx, implicit $eax

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