MIPS: Support '%w' token in inline asm template for MSA

MSA registers share the FPRs as its bottom half. So that we can use
MSA instructions to work with normal float/double:
   double a, b, c;
   asm volatile ("fmadd.d %w0, %w1, %w2" : "+f"(a) : "f"(b), "f"(c));

GCC has support it for quite long time.

Author: wzssyqa

llvm/lib/Target/Mips/MipsAsmPrinter.cpp

@@ -565,12 +565,27 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
       }
       break;
     }
-    case 'w':
-      // Print MSA registers for the 'f' constraint
-      // In LLVM, the 'w' modifier doesn't need to do anything.
-      // We can just call printOperand as normal.
+    case 'w': {
+      // Support to use MSA instructions on FPR.
+      // double a, b, c;
+      // asm volatile ("fmadd.d %w0, %w1, %w2" : "+f"(a) : "f"(b), "f"(c))
+      const char *RegNameF =
+          MipsInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
+      if (RegNameF[0] != 'f')
+        break;
+      // Now we have 'fXX', let's find 'wXX'.
+      for (const char *RegNameW = RegNameF; RegNameW < RegNameF + 32;
+           RegNameW++) {
+        if (RegNameW[0] != 'w')
+          continue;
+        if (StringRef(RegNameF + 1) == StringRef(RegNameW + 1)) {
+          O << '$' << RegNameW;
+          return false;
+        }
+      }
       break;
     }
+    }
   }
 
   printOperand(MI, OpNum, O);

llvm/test/CodeGen/Mips/msa/inline-asm.ll

@@ -32,3 +32,11 @@ entry:
   store <4 x i32> %1, ptr @v4i32_r
   ret void
 }
+
+define dso_local double @test4(double noundef %a, double noundef %b, double noundef %c) {
+entry:
+  ; CHECK-LABEL: test4:
+  %0 = tail call double asm sideeffect "fmadd.d ${0:w}, ${1:w}, ${2:w}", "=f,f,f,0,~{$1}"(double %b, double %c, double %a)
+  ; CHECK: fmadd.d $w{{([0-9]|[1-3][0-9])}}, $w{{([0-9]|[1-3][0-9])}}, $w{{([0-9]|[1-3][0-9])}}
+  ret double %0
+}