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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 |
| 2 | +; RUN: llc -relocation-model=static < %s | FileCheck %s |
| 3 | + |
| 4 | +target triple = "armv7a-linux-gnueabi" |
| 5 | + |
| 6 | +define i32 @test1() #0 { |
| 7 | +; CHECK-LABEL: test1: |
| 8 | +; CHECK: @ %bb.0: |
| 9 | +; CHECK-NEXT: push {r11, lr} |
| 10 | +; CHECK-NEXT: sub sp, sp, #8 |
| 11 | +; CHECK-NEXT: sub sp, sp, #1024 |
| 12 | +; CHECK-NEXT: movw r0, :lower16:__stack_chk_guard |
| 13 | +; CHECK-NEXT: movt r0, :upper16:__stack_chk_guard |
| 14 | +; CHECK-NEXT: ldr r0, [r0] |
| 15 | +; CHECK-NEXT: ldr r0, [r0] |
| 16 | +; CHECK-NEXT: str r0, [sp, #1028] |
| 17 | +; CHECK-NEXT: add r0, sp, #4 |
| 18 | +; CHECK-NEXT: bl foo |
| 19 | +; CHECK-NEXT: movw r1, :lower16:__stack_chk_guard |
| 20 | +; CHECK-NEXT: ldr r0, [sp, #1028] |
| 21 | +; CHECK-NEXT: movt r1, :upper16:__stack_chk_guard |
| 22 | +; CHECK-NEXT: ldr r1, [r1] |
| 23 | +; CHECK-NEXT: ldr r1, [r1] |
| 24 | +; CHECK-NEXT: cmp r1, r0 |
| 25 | +; CHECK-NEXT: moveq r0, #0 |
| 26 | +; CHECK-NEXT: addeq sp, sp, #8 |
| 27 | +; CHECK-NEXT: addeq sp, sp, #1024 |
| 28 | +; CHECK-NEXT: popeq {r11, pc} |
| 29 | +; CHECK-NEXT: .LBB0_1: |
| 30 | +; CHECK-NEXT: bl __stack_chk_fail |
| 31 | + %a1 = alloca [256 x i32], align 4 |
| 32 | + call void @foo(ptr %a1) #3 |
| 33 | + ret i32 0 |
| 34 | +} |
| 35 | + |
| 36 | +declare void @foo(ptr) |
| 37 | + |
| 38 | +attributes #0 = { nounwind sspstrong } |
| 39 | + |
| 40 | +!llvm.module.flags = !{!0} |
| 41 | +!0 = !{i32 8, !"PIC Level", i32 2} |
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