Fixups

Author: MacDue

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

@@ -546,12 +546,25 @@ bool AArch64FrameLowering::hasFPImpl(const MachineFunction &MF) const {
       MFI.hasStackMap() || MFI.hasPatchPoint() ||
       RegInfo->hasStackRealignment(MF))
     return true;
-  // If we have streaming mode changes and SVE registers on the stack we need a
-  // FP. This is as the stack size may depend on the VG at entry to the
-  // function, which is saved before the SVE area (so unrecoverable without a
-  // FP). Similar for locally streaming functions, but it is because we use
-  // ADDSVL to setup the SVE stack (which might not match VG, even without
-  // streaming-mode changes).
+
+  // If we:
+  //
+  //   1. Have streaming mode changes
+  //     OR:
+  //   2. Have a streaming body with SVE stack objects
+  //
+  // Then the value of VG restored when unwinding to this function may not match
+  // the value of VG used to set up the stack.
+  //
+  // This is a problem as the CFA can be described with an expression of the
+  // form: CFA = SP + NumBytes + VG * NumScalableBytes.
+  //
+  // If the value of VG used in that expression does not match the value used to
+  // set up the stack, an incorrect address for the CFA will be computed, and
+  // unwinding will fail.
+  //
+  // We work around this issue by ensuring the frame-pointer can describe the
+  // CFA in either of these cases.
   if (AFI.needsDwarfUnwindInfo(MF) &&
       ((requiresSaveVG(MF) || AFI.getSMEFnAttrs().hasStreamingBody()) &&
        (!AFI.hasCalculatedStackSizeSVE() || AFI.getStackSizeSVE() > 0)))
@@ -1498,7 +1511,7 @@ bool isVGInstruction(MachineBasicBlock::iterator MBBI,
   if (Opc == AArch64::BL)
     return matchLibcall(TLI, MBBI->getOperand(0), RTLIB::SMEABI_GET_CURRENT_VG);
 
-  return Opc == AArch64::ORRXrr;
+  return Opc == TargetOpcode::COPY;
 }
 
 // Convert callee-save register save/restore instruction to do stack pointer
@@ -3548,10 +3561,8 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
     unsigned X0Scratch = AArch64::NoRegister;
     auto RestoreX0 = make_scope_exit([&] {
       if (X0Scratch != AArch64::NoRegister)
-        BuildMI(MBB, MI, DL, TII.get(AArch64::ORRXrr), AArch64::X0)
-            .addReg(AArch64::XZR)
-            .addReg(X0Scratch, RegState::Undef)
-            .addReg(X0Scratch, RegState::Implicit)
+        BuildMI(MBB, MI, DL, TII.get(TargetOpcode::COPY), AArch64::X0)
+            .addReg(X0Scratch)
             .setMIFlag(MachineInstr::FrameSetup);
     });
 
@@ -3570,15 +3581,12 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
                    [&STI](const MachineBasicBlock::RegisterMaskPair &LiveIn) {
                      return STI.getRegisterInfo()->isSuperOrSubRegisterEq(
                          AArch64::X0, LiveIn.PhysReg);
-                   }))
+                   })) {
           X0Scratch = Reg1;
-
-        if (X0Scratch != AArch64::NoRegister)
-          BuildMI(MBB, MI, DL, TII.get(AArch64::ORRXrr), Reg1)
-              .addReg(AArch64::XZR)
-              .addReg(AArch64::X0, RegState::Undef)
-              .addReg(AArch64::X0, RegState::Implicit)
+          BuildMI(MBB, MI, DL, TII.get(TargetOpcode::COPY), X0Scratch)
+              .addReg(AArch64::X0)
               .setMIFlag(MachineInstr::FrameSetup);
+        }
 
         RTLIB::Libcall LC = RTLIB::SMEABI_GET_CURRENT_VG;
         const uint32_t *RegMask =
@@ -4214,16 +4222,11 @@ bool AArch64FrameLowering::assignCalleeSavedSpillSlots(
   // Insert VG into the list of CSRs, immediately before LR if saved.
   if (requiresSaveVG(MF)) {
     CalleeSavedInfo VGInfo(AArch64::VG);
-
-    bool InsertedBeforeLR = false;
-    for (unsigned I = 0; I < CSI.size(); I++)
-      if (CSI[I].getReg() == AArch64::LR) {
-        InsertedBeforeLR = true;
-        CSI.insert(CSI.begin() + I, VGInfo);
-        break;
-      }
-
-    if (!InsertedBeforeLR)
+    auto It =
+        find_if(CSI, [](auto &Info) { return Info.getReg() == AArch64::LR; });
+    if (It != CSI.end())
+      CSI.insert(It, VGInfo);
+    else
       CSI.push_back(VGInfo);
   }
 

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

@@ -6002,12 +6002,13 @@ llvm::createCFAOffset(const TargetRegisterInfo &TRI, unsigned Reg,
   assert(NumVGScaledBytes && "Expected scalable offset");
   SmallString<64> OffsetExpr;
   // + VG * NumVGScaledBytes
-  StringRef VGRegScale("* VG");
+  StringRef VGRegScale;
   if (IncomingVGOffsetFromDefCFA) {
     appendLoadRegExpr(OffsetExpr, *IncomingVGOffsetFromDefCFA);
     VGRegScale = "* IncomingVG";
   } else {
     appendReadRegExpr(OffsetExpr, TRI.getDwarfRegNum(AArch64::VG, true));
+    VGRegScale = "* VG";
   }
   appendConstantExpr(OffsetExpr, NumVGScaledBytes, dwarf::DW_OP_mul);
   appendOffsetComment(NumVGScaledBytes, Comment, VGRegScale);