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[AMDGPU][MC] GFX9 - allow op_sel in v_interp_p2_f16 (#150712)
AMDGPU documentation states op_sel[3] can be used in v_interp_p2_f16 in GFX9.
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6 files changed

+236
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‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 40 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1944,6 +1944,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
19441944

19451945
void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
19461946
void cvtVINTERP(MCInst &Inst, const OperandVector &Operands);
1947+
void cvtOpSelHelper(MCInst &Inst, unsigned OpSel);
19471948

19481949
bool parseDimId(unsigned &Encoding);
19491950
ParseStatus parseDim(OperandVector &Operands);
@@ -9239,6 +9240,33 @@ static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) {
92399240
MCOI::OperandConstraint::TIED_TO) == -1;
92409241
}
92419242

9243+
void AMDGPUAsmParser::cvtOpSelHelper(MCInst &Inst, unsigned OpSel) {
9244+
unsigned Opc = Inst.getOpcode();
9245+
constexpr AMDGPU::OpName Ops[] = {AMDGPU::OpName::src0, AMDGPU::OpName::src1,
9246+
AMDGPU::OpName::src2};
9247+
constexpr AMDGPU::OpName ModOps[] = {AMDGPU::OpName::src0_modifiers,
9248+
AMDGPU::OpName::src1_modifiers,
9249+
AMDGPU::OpName::src2_modifiers};
9250+
for (int J = 0; J < 3; ++J) {
9251+
int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]);
9252+
if (OpIdx == -1)
9253+
// Some instructions, e.g. v_interp_p2_f16 in GFX9, have src0, src2, but
9254+
// no src1. So continue instead of break.
9255+
continue;
9256+
9257+
int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);
9258+
uint32_t ModVal = Inst.getOperand(ModIdx).getImm();
9259+
9260+
if ((OpSel & (1 << J)) != 0)
9261+
ModVal |= SISrcMods::OP_SEL_0;
9262+
// op_sel[3] is encoded in src0_modifiers.
9263+
if (ModOps[J] == AMDGPU::OpName::src0_modifiers && (OpSel & (1 << 3)) != 0)
9264+
ModVal |= SISrcMods::DST_OP_SEL;
9265+
9266+
Inst.getOperand(ModIdx).setImm(ModVal);
9267+
}
9268+
}
9269+
92429270
void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
92439271
{
92449272
OptionalImmIndexMap OptionalIdx;
@@ -9275,6 +9303,16 @@ void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
92759303
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
92769304
addOptionalImmOperand(Inst, Operands, OptionalIdx,
92779305
AMDGPUOperand::ImmTyOModSI);
9306+
9307+
// Some v_interp instructions use op_sel[3] for dst.
9308+
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
9309+
addOptionalImmOperand(Inst, Operands, OptionalIdx,
9310+
AMDGPUOperand::ImmTyOpSel);
9311+
int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
9312+
unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
9313+
9314+
cvtOpSelHelper(Inst, OpSel);
9315+
}
92789316
}
92799317

92809318
void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)
@@ -9310,31 +9348,10 @@ void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)
93109348
if (OpSelIdx == -1)
93119349
return;
93129350

9313-
const AMDGPU::OpName Ops[] = {AMDGPU::OpName::src0, AMDGPU::OpName::src1,
9314-
AMDGPU::OpName::src2};
9315-
const AMDGPU::OpName ModOps[] = {AMDGPU::OpName::src0_modifiers,
9316-
AMDGPU::OpName::src1_modifiers,
9317-
AMDGPU::OpName::src2_modifiers};
9318-
93199351
unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
9320-
9321-
for (int J = 0; J < 3; ++J) {
9322-
int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]);
9323-
if (OpIdx == -1)
9324-
break;
9325-
9326-
int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);
9327-
uint32_t ModVal = Inst.getOperand(ModIdx).getImm();
9328-
9329-
if ((OpSel & (1 << J)) != 0)
9330-
ModVal |= SISrcMods::OP_SEL_0;
9331-
if (ModOps[J] == AMDGPU::OpName::src0_modifiers &&
9332-
(OpSel & (1 << 3)) != 0)
9333-
ModVal |= SISrcMods::DST_OP_SEL;
9334-
9335-
Inst.getOperand(ModIdx).setImm(ModVal);
9336-
}
9352+
cvtOpSelHelper(Inst, OpSel);
93379353
}
9354+
93389355
void AMDGPUAsmParser::cvtScaledMFMA(MCInst &Inst,
93399356
const OperandVector &Operands) {
93409357
OptionalImmIndexMap OptionalIdx;

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1280,6 +1280,17 @@ void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
12801280
(ModIdx != -1) ? MI->getOperand(ModIdx).getImm() : DefaultValue;
12811281
}
12821282

1283+
// Some instructions, e.g. v_interp_p2_f16 in GFX9, have src0, src2, but no
1284+
// src1.
1285+
if (NumOps == 1 && AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src2) &&
1286+
!AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1)) {
1287+
Ops[NumOps++] = DefaultValue; // Set src1_modifiers to default.
1288+
int Mod2Idx =
1289+
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers);
1290+
assert(Mod2Idx != -1);
1291+
Ops[NumOps++] = MI->getOperand(Mod2Idx).getImm();
1292+
}
1293+
12831294
const bool HasDst =
12841295
(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst) != -1) ||
12851296
(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst) != -1);

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td‎

Lines changed: 22 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,7 @@ class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> :
9797
VOP3_Pseudo<OpName, P, pattern> {
9898
let AsmMatchConverter = "cvtVOP3Interp";
9999
let mayRaiseFPException = 0;
100+
let VOP3_OPSEL = P.HasOpSel;
100101
}
101102

102103
def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
@@ -119,16 +120,17 @@ def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
119120
let HasSrc0Mods = 0;
120121
}
121122

122-
class getInterp16Asm <bit HasSrc2, bit HasOMod> {
123+
class getInterp16Asm <bit HasSrc2, bit HasOMod, bit OpSel> {
123124
string src2 = !if(HasSrc2, ", $src2_modifiers", "");
124125
string omod = !if(HasOMod, "$omod", "");
126+
string opsel = !if(OpSel, "$op_sel", "");
125127
string ret =
126-
" $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod;
128+
" $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod#opsel;
127129
}
128130

129131
class getInterp16Ins <bit HasSrc2, bit HasOMod,
130-
Operand Src0Mod, Operand Src2Mod> {
131-
dag ret = !if(HasSrc2,
132+
Operand Src0Mod, Operand Src2Mod, bit OpSel> {
133+
dag ret1 = !if(HasSrc2,
132134
!if(HasOMod,
133135
(ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
134136
InterpAttr:$attr, InterpAttrChan:$attrchan,
@@ -143,19 +145,22 @@ class getInterp16Ins <bit HasSrc2, bit HasOMod,
143145
InterpAttr:$attr, InterpAttrChan:$attrchan,
144146
highmod:$high, Clamp0:$clamp, omod0:$omod)
145147
);
148+
dag ret2 = !if(OpSel, (ins op_sel0:$op_sel), (ins));
149+
dag ret = !con(ret1, ret2);
146150
}
147151

148-
class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
152+
class VOP3_INTERP16 <list<ValueType> ArgVT, bit OpSel = 0> : VOPProfile<ArgVT> {
149153
let IsSingle = 1;
150154
let HasOMod = !ne(DstVT.Value, f16.Value);
151155
let HasHigh = 1;
156+
let HasOpSel = OpSel;
152157

153158
let Src0Mod = FPVRegInputMods;
154159
let Src2Mod = FPVRegInputMods;
155160

156161
let Outs64 = (outs DstRC.RegClass:$vdst);
157-
let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret;
158-
let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret;
162+
let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod, OpSel>.ret;
163+
let Asm64 = getInterp16Asm<HasSrc2, HasOMod, OpSel>.ret;
159164
}
160165

161166
//===----------------------------------------------------------------------===//
@@ -480,7 +485,7 @@ let SubtargetPredicate = isGFX9Plus in {
480485
defm V_MAD_U16_gfx9 : VOP3Inst_t16 <"v_mad_u16_gfx9", VOP_I16_I16_I16_I16>;
481486
defm V_MAD_I16_gfx9 : VOP3Inst_t16 <"v_mad_i16_gfx9", VOP_I16_I16_I16_I16>;
482487
let OtherPredicates = [isNotGFX90APlus] in
483-
def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>;
488+
def V_INTERP_P2_F16_opsel : VOP3Interp <"v_interp_p2_f16_opsel", VOP3_INTERP16<[f16, f32, i32, f32], /*OpSel*/ 1>>;
484489
} // End SubtargetPredicate = isGFX9Plus
485490

486491
// This predicate should only apply to the selection pattern. The
@@ -2676,6 +2681,14 @@ multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName>
26762681
}
26772682
}
26782683

2684+
multiclass VOP3Interp_F16_OpSel_Real_gfx9<bits<10> op, string OpName, string AsmName> {
2685+
def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
2686+
VOP3Interp_OpSel_gfx9 <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
2687+
VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
2688+
let AsmString = AsmName # ps.AsmOperands;
2689+
}
2690+
}
2691+
26792692
multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
26802693
def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
26812694
VOP3e_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl> {
@@ -2788,7 +2801,7 @@ defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">;
27882801
defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">;
27892802
defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">;
27902803
defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">;
2791-
defm V_INTERP_P2_F16_gfx9 : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">;
2804+
defm V_INTERP_P2_F16_opsel : VOP3Interp_F16_OpSel_Real_gfx9 <0x277, "V_INTERP_P2_F16_opsel", "v_interp_p2_f16">;
27922805

27932806
defm V_ADD_I32 : VOP3_Real_vi <0x29c>;
27942807
defm V_SUB_I32 : VOP3_Real_vi <0x29d>;

‎llvm/lib/Target/AMDGPU/VOPInstructions.td‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -419,6 +419,13 @@ class VOP3a_ScaleSel_gfx1250<bits<10> op, VOPProfile p> : VOP3e_gfx11_gfx12<op,
419419
let Inst{14-11} = scale_sel;
420420
}
421421

422+
class VOP3Interp_OpSel_gfx9<bits<10> op, VOPProfile p> : VOP3Interp_vi<op, p> {
423+
let Inst{11} = src0_modifiers{2};
424+
// There's no src1
425+
let Inst{13} = src2_modifiers{2};
426+
let Inst{14} = !if(p.HasDst, src0_modifiers{3}, 0);
427+
}
428+
422429
class VOP3Interp_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> {
423430
bits<6> attr;
424431
bits<2> attrchan;

‎llvm/test/MC/AMDGPU/vop3-gfx9.s‎

Lines changed: 135 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -566,6 +566,141 @@ v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
566566
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
567567
// VI: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
568568

569+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,0]
570+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04]
571+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
572+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
573+
574+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,1]
575+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x77,0xd2,0x00,0x04,0x0e,0x04]
576+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
577+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
578+
579+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,1,0]
580+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04]
581+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
582+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
583+
584+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,1,1]
585+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x77,0xd2,0x00,0x04,0x0e,0x04]
586+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
587+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
588+
589+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,0]
590+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x77,0xd2,0x00,0x04,0x0e,0x04]
591+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
592+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
593+
594+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,1]
595+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,1,0] ; encoding: [0x05,0x28,0x77,0xd2,0x00,0x04,0x0e,0x04]
596+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
597+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
598+
599+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,1,1]
600+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x77,0xd2,0x00,0x04,0x0e,0x04]
601+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
602+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
603+
604+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,0]
605+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x77,0xd2,0x00,0x04,0x0e,0x04]
606+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
607+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
608+
609+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,1]
610+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,1,0] ; encoding: [0x05,0x28,0x77,0xd2,0x00,0x04,0x0e,0x04]
611+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
612+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
613+
614+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,1,0]
615+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x77,0xd2,0x00,0x04,0x0e,0x04]
616+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
617+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
618+
619+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,1,1]
620+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,1,0] ; encoding: [0x05,0x28,0x77,0xd2,0x00,0x04,0x0e,0x04]
621+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
622+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
623+
624+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,0,0]
625+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04]
626+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
627+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
628+
629+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,0,1]
630+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x77,0xd2,0x00,0x04,0x0e,0x04]
631+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
632+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
633+
634+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,1,0]
635+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x77,0xd2,0x00,0x04,0x0e,0x04]
636+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
637+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
638+
639+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,1,1]
640+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,1,1] ; encoding: [0x05,0x60,0x77,0xd2,0x00,0x04,0x0e,0x04]
641+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
642+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
643+
644+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,1,0,0]
645+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04]
646+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
647+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
648+
649+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,1,0,1]
650+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x77,0xd2,0x00,0x04,0x0e,0x04]
651+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
652+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
653+
654+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,1,1,0]
655+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x77,0xd2,0x00,0x04,0x0e,0x04]
656+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
657+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
658+
659+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,1,1,1]
660+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,1,1] ; encoding: [0x05,0x60,0x77,0xd2,0x00,0x04,0x0e,0x04]
661+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
662+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
663+
664+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,0,0]
665+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x77,0xd2,0x00,0x04,0x0e,0x04]
666+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
667+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
668+
669+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,0,1]
670+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,0,1] ; encoding: [0x05,0x48,0x77,0xd2,0x00,0x04,0x0e,0x04]
671+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
672+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
673+
674+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,1,0]
675+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,1,0] ; encoding: [0x05,0x28,0x77,0xd2,0x00,0x04,0x0e,0x04]
676+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
677+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
678+
679+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,1,1]
680+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,1,1] ; encoding: [0x05,0x68,0x77,0xd2,0x00,0x04,0x0e,0x04]
681+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
682+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
683+
684+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,1,0,0]
685+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x77,0xd2,0x00,0x04,0x0e,0x04]
686+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
687+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
688+
689+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,1,0,1]
690+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,0,1] ; encoding: [0x05,0x48,0x77,0xd2,0x00,0x04,0x0e,0x04]
691+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
692+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
693+
694+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,1,1,0]
695+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,1,0] ; encoding: [0x05,0x28,0x77,0xd2,0x00,0x04,0x0e,0x04]
696+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
697+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
698+
699+
v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,1,1,1]
700+
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,1,1] ; encoding: [0x05,0x68,0x77,0xd2,0x00,0x04,0x0e,0x04]
701+
// NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
702+
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: not a valid operand.
703+
569704
v_interp_p2_legacy_f16 v5, v2, attr31.x, v3
570705
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr31.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x1f,0x04,0x0e,0x04]
571706
// NOGCN: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU

‎llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19311,6 +19311,27 @@
1931119311
# CHECK: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x77,0xd2,0x00,0x04,0x0e,0x04]
1931219312
0x05,0x80,0x77,0xd2,0x00,0x04,0x0e,0x04
1931319313

19314+
# CHECK: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x77,0xd2,0x00,0x04,0x0e,0x04]
19315+
0x05,0x40,0x77,0xd2,0x00,0x04,0x0e,0x04
19316+
19317+
# CHECK: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x77,0xd2,0x00,0x04,0x0e,0x04]
19318+
0x05,0x20,0x77,0xd2,0x00,0x04,0x0e,0x04
19319+
19320+
# CHECK: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,1,1] ; encoding: [0x05,0x60,0x77,0xd2,0x00,0x04,0x0e,0x04]
19321+
0x05,0x60,0x77,0xd2,0x00,0x04,0x0e,0x04
19322+
19323+
# CHECK: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x77,0xd2,0x00,0x04,0x0e,0x04]
19324+
0x05,0x08,0x77,0xd2,0x00,0x04,0x0e,0x04
19325+
19326+
# CHECK: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,0,1] ; encoding: [0x05,0x48,0x77,0xd2,0x00,0x04,0x0e,0x04]
19327+
0x05,0x48,0x77,0xd2,0x00,0x04,0x0e,0x04
19328+
19329+
# CHECK: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,1,0] ; encoding: [0x05,0x28,0x77,0xd2,0x00,0x04,0x0e,0x04]
19330+
0x05,0x28,0x77,0xd2,0x00,0x04,0x0e,0x04
19331+
19332+
# CHECK: v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1,0,1,1] ; encoding: [0x05,0x68,0x77,0xd2,0x00,0x04,0x0e,0x04]
19333+
0x05,0x68,0x77,0xd2,0x00,0x04,0x0e,0x04
19334+
1931419335
# CHECK: v_add_f64 v[5:6], v[1:2], v[2:3] ; encoding: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x00]
1931519336
0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x00
1931619337

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