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[RISCV][SiFive] Support Xsfvfwmaccqqq extensions
Bfloat16 Matrix Multiply Accumulate Instruction https://sifive.cdn.prismic.io/sifive/c391d53e-ffcf-4091-82f6-c37bf3e883ed_xsfvfwmaccqqq-spec.pdf
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lines changed

19 files changed

+523
-12
lines changed

‎clang/include/clang/Basic/riscv_sifive_vector.td‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,14 @@ let SupportOverloading = false in {
104104
}
105105
}
106106

107+
multiclass RVVVFWMACCBuiltinSet<list<list<string>> suffixes_prototypes> {
108+
let OverloadedName = NAME,
109+
Name = NAME,
110+
HasMasked = false,
111+
Log2LMUL = [-2, -1, 0, 1, 2] in
112+
defm NAME : RVVOutOp1Op2BuiltinSet<NAME, "x", suffixes_prototypes>;
113+
}
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107115
multiclass RVVVQMACCBuiltinSet<list<list<string>> suffixes_prototypes> {
108116
let OverloadedName = NAME,
109117
Name = NAME,
@@ -127,3 +135,7 @@ let UnMaskedPolicyScheme = HasPolicyOperand in
127135
defm sf_vqmaccus_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
128136
defm sf_vqmaccsu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
129137
}
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139+
let UnMaskedPolicyScheme = HasPolicyOperand in
140+
let RequiredFeatures = ["Xsfvfwmaccqqq"] in
141+
defm sf_vfwmacc_4x4x4 : RVVVFWMACCBuiltinSet<[["", "w", "wwSvv"]]>;

‎clang/include/clang/Support/RISCVVIntrinsicUtils.h‎

Lines changed: 12 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -485,17 +485,18 @@ enum RVVRequire : uint16_t {
485485
RVV_REQ_RV64 = 1 << 0,
486486
RVV_REQ_ZvfhminOrZvfh = 1 << 1,
487487
RVV_REQ_Xsfvcp = 1 << 2,
488-
RVV_REQ_Xsfvqmaccdod = 1 << 3,
489-
RVV_REQ_Xsfvqmaccqoq = 1 << 4,
490-
RVV_REQ_Zvbb = 1 << 5,
491-
RVV_REQ_Zvbc = 1 << 6,
492-
RVV_REQ_Zvkb = 1 << 7,
493-
RVV_REQ_Zvkg = 1 << 8,
494-
RVV_REQ_Zvkned = 1 << 9,
495-
RVV_REQ_Zvknha = 1 << 10,
496-
RVV_REQ_Zvknhb = 1 << 11,
497-
RVV_REQ_Zvksed = 1 << 12,
498-
RVV_REQ_Zvksh = 1 << 13,
488+
RVV_REQ_Xsfvfwmaccqqq = 1 << 3,
489+
RVV_REQ_Xsfvqmaccdod = 1 << 4,
490+
RVV_REQ_Xsfvqmaccqoq = 1 << 5,
491+
RVV_REQ_Zvbb = 1 << 6,
492+
RVV_REQ_Zvbc = 1 << 7,
493+
RVV_REQ_Zvkb = 1 << 8,
494+
RVV_REQ_Zvkg = 1 << 9,
495+
RVV_REQ_Zvkned = 1 << 10,
496+
RVV_REQ_Zvknha = 1 << 11,
497+
RVV_REQ_Zvknhb = 1 << 12,
498+
RVV_REQ_Zvksed = 1 << 13,
499+
RVV_REQ_Zvksh = 1 << 14,
499500

500501
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Zvksh)
501502
};

‎clang/lib/Sema/SemaRISCVVectorLookup.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -205,6 +205,7 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
205205
static const std::pair<const char *, RVVRequire> FeatureCheckList[] = {
206206
{"64bit", RVV_REQ_RV64},
207207
{"xsfvcp", RVV_REQ_Xsfvcp},
208+
{"xsfvfwmaccqqq", RVV_REQ_Xsfvfwmaccqqq},
208209
{"xsfvqmaccdod", RVV_REQ_Xsfvqmaccdod},
209210
{"xsfvqmaccqoq", RVV_REQ_Xsfvqmaccqoq},
210211
{"experimental-zvbb", RVV_REQ_Zvbb},

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c‎

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2+
// REQUIRES: riscv-registered-target
3+
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvfh -target-feature +xsfvfwmaccqqq \
4+
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \
5+
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
6+
7+
#include <sifive_vector.h>
8+
9+
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2
10+
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
11+
// CHECK-RV64-NEXT: entry:
12+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4f16.nxv1f16.i64(<vscale x 1 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3)
13+
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
14+
//
15+
vfloat32mf2_t test_sf_vfwmacc_4x4x4_f32mf2(vfloat32mf2_t vd, vfloat16m1_t vs1, vfloat16mf4_t vs2, size_t vl) {
16+
return __riscv_sf_vfwmacc_4x4x4_f32mf2(vd, vs1, vs2, vl);
17+
}
18+
19+
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1
20+
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
21+
// CHECK-RV64-NEXT: entry:
22+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4f16.nxv2f16.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3)
23+
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
24+
//
25+
vfloat32m1_t test_sf_vfwmacc_4x4x4_f32m1(vfloat32m1_t vd, vfloat16m1_t vs1, vfloat16mf2_t vs2, size_t vl) {
26+
return __riscv_sf_vfwmacc_4x4x4_f32m1(vd, vs1, vs2, vl);
27+
}
28+
29+
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2
30+
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
31+
// CHECK-RV64-NEXT: entry:
32+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3)
33+
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
34+
//
35+
vfloat32m2_t test_sf_vfwmacc_4x4x4_f32m2(vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
36+
return __riscv_sf_vfwmacc_4x4x4_f32m2(vd, vs1, vs2, vl);
37+
}
38+
39+
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4
40+
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
41+
// CHECK-RV64-NEXT: entry:
42+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4f16.nxv8f16.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3)
43+
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
44+
//
45+
vfloat32m4_t test_sf_vfwmacc_4x4x4_f32m4(vfloat32m4_t vd, vfloat16m1_t vs1, vfloat16m2_t vs2, size_t vl) {
46+
return __riscv_sf_vfwmacc_4x4x4_f32m4(vd, vs1, vs2, vl);
47+
}
48+
49+
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8
50+
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
51+
// CHECK-RV64-NEXT: entry:
52+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4f16.nxv16f16.i64(<vscale x 16 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3)
53+
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
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//
55+
vfloat32m8_t test_sf_vfwmacc_4x4x4_f32m8(vfloat32m8_t vd, vfloat16m1_t vs1, vfloat16m4_t vs2, size_t vl) {
56+
return __riscv_sf_vfwmacc_4x4x4_f32m8(vd, vs1, vs2, vl);
57+
}

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vfwmacc_4x4x4.c‎

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2+
// REQUIRES: riscv-registered-target
3+
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvfh -target-feature +xsfvfwmaccqqq \
4+
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \
5+
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
6+
7+
#include <sifive_vector.h>
8+
9+
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2
10+
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
11+
// CHECK-RV64-NEXT: entry:
12+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4f16.nxv1f16.i64(<vscale x 1 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3)
13+
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
14+
//
15+
vfloat32mf2_t test_sf_vfwmacc_4x4x4_f32mf2(vfloat32mf2_t vd, vfloat16m1_t vs1, vfloat16mf4_t vs2, size_t vl) {
16+
return __riscv_sf_vfwmacc_4x4x4(vd, vs1, vs2, vl);
17+
}
18+
19+
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1
20+
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
21+
// CHECK-RV64-NEXT: entry:
22+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4f16.nxv2f16.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3)
23+
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
24+
//
25+
vfloat32m1_t test_sf_vfwmacc_4x4x4_f32m1(vfloat32m1_t vd, vfloat16m1_t vs1, vfloat16mf2_t vs2, size_t vl) {
26+
return __riscv_sf_vfwmacc_4x4x4(vd, vs1, vs2, vl);
27+
}
28+
29+
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2
30+
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
31+
// CHECK-RV64-NEXT: entry:
32+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3)
33+
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
34+
//
35+
vfloat32m2_t test_sf_vfwmacc_4x4x4_f32m2(vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
36+
return __riscv_sf_vfwmacc_4x4x4(vd, vs1, vs2, vl);
37+
}
38+
39+
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4
40+
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
41+
// CHECK-RV64-NEXT: entry:
42+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4f16.nxv8f16.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3)
43+
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
44+
//
45+
vfloat32m4_t test_sf_vfwmacc_4x4x4_f32m4(vfloat32m4_t vd, vfloat16m1_t vs1, vfloat16m2_t vs2, size_t vl) {
46+
return __riscv_sf_vfwmacc_4x4x4(vd, vs1, vs2, vl);
47+
}
48+
49+
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8
50+
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
51+
// CHECK-RV64-NEXT: entry:
52+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4f16.nxv16f16.i64(<vscale x 16 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3)
53+
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
54+
//
55+
vfloat32m8_t test_sf_vfwmacc_4x4x4_f32m8(vfloat32m8_t vd, vfloat16m1_t vs1, vfloat16m4_t vs2, size_t vl) {
56+
return __riscv_sf_vfwmacc_4x4x4(vd, vs1, vs2, vl);
57+
}

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vfwmacc_4x4x4.c‎

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2+
// REQUIRES: riscv-registered-target
3+
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvfh -target-feature +xsfvfwmaccqqq \
4+
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \
5+
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
6+
7+
#include <sifive_vector.h>
8+
9+
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2_tu
10+
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
11+
// CHECK-RV64-NEXT: entry:
12+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4f16.nxv1f16.i64(<vscale x 1 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2)
13+
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
14+
//
15+
vfloat32mf2_t test_sf_vfwmacc_4x4x4_f32mf2_tu(vfloat32mf2_t vd, vfloat16m1_t vs1, vfloat16mf4_t vs2, size_t vl) {
16+
return __riscv_sf_vfwmacc_4x4x4_f32mf2_tu(vd, vs1, vs2, vl);
17+
}
18+
19+
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1
20+
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
21+
// CHECK-RV64-NEXT: entry:
22+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4f16.nxv2f16.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2)
23+
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
24+
//
25+
vfloat32m1_t test_sf_vfwmacc_4x4x4_f32m1(vfloat32m1_t vd, vfloat16m1_t vs1, vfloat16mf2_t vs2, size_t vl) {
26+
return __riscv_sf_vfwmacc_4x4x4_f32m1_tu(vd, vs1, vs2, vl);
27+
}
28+
29+
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2
30+
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
31+
// CHECK-RV64-NEXT: entry:
32+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2)
33+
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
34+
//
35+
vfloat32m2_t test_sf_vfwmacc_4x4x4_f32m2(vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
36+
return __riscv_sf_vfwmacc_4x4x4_f32m2_tu(vd, vs1, vs2, vl);
37+
}
38+
39+
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4
40+
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
41+
// CHECK-RV64-NEXT: entry:
42+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4f16.nxv8f16.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2)
43+
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
44+
//
45+
vfloat32m4_t test_sf_vfwmacc_4x4x4_f32m4(vfloat32m4_t vd, vfloat16m1_t vs1, vfloat16m2_t vs2, size_t vl) {
46+
return __riscv_sf_vfwmacc_4x4x4_f32m4_tu(vd, vs1, vs2, vl);
47+
}
48+
49+
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8
50+
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4f16.nxv16f16.i64(<vscale x 16 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2)
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// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
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//
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vfloat32m8_t test_sf_vfwmacc_4x4x4_f32m8(vfloat32m8_t vd, vfloat16m1_t vs1, vfloat16m4_t vs2, size_t vl) {
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return __riscv_sf_vfwmacc_4x4x4_f32m8_tu(vd, vs1, vs2, vl);
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}

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vfwmacc_4x4x4.c‎

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
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// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvfh -target-feature +xsfvfwmaccqqq \
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// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \
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// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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#include <sifive_vector.h>
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// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2_tu
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// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4f16.nxv1f16.i64(<vscale x 1 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2)
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// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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//
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vfloat32mf2_t test_sf_vfwmacc_4x4x4_f32mf2_tu(vfloat32mf2_t vd, vfloat16m1_t vs1, vfloat16mf4_t vs2, size_t vl) {
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return __riscv_sf_vfwmacc_4x4x4_tu(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1
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// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4f16.nxv2f16.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2)
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// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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//
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vfloat32m1_t test_sf_vfwmacc_4x4x4_f32m1(vfloat32m1_t vd, vfloat16m1_t vs1, vfloat16mf2_t vs2, size_t vl) {
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return __riscv_sf_vfwmacc_4x4x4_tu(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2
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// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
31+
// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2)
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// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
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//
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vfloat32m2_t test_sf_vfwmacc_4x4x4_f32m2(vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
36+
return __riscv_sf_vfwmacc_4x4x4_tu(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4
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// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
41+
// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4f16.nxv8f16.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2)
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// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
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//
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vfloat32m4_t test_sf_vfwmacc_4x4x4_f32m4(vfloat32m4_t vd, vfloat16m1_t vs1, vfloat16m2_t vs2, size_t vl) {
46+
return __riscv_sf_vfwmacc_4x4x4_tu(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8
50+
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
51+
// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4f16.nxv16f16.i64(<vscale x 16 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2)
53+
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
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//
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vfloat32m8_t test_sf_vfwmacc_4x4x4_f32m8(vfloat32m8_t vd, vfloat16m1_t vs1, vfloat16m4_t vs2, size_t vl) {
56+
return __riscv_sf_vfwmacc_4x4x4_tu(vd, vs1, vs2, vl);
57+
}

‎clang/test/Preprocessor/riscv-target-features.c‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@
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// CHECK-NOT: __riscv_xcvsimd {{.*$}}
3434
// CHECK-NOT: __riscv_xsfcie {{.*$}}
3535
// CHECK-NOT: __riscv_xsfvcp {{.*$}}
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// CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
3637
// CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
3738
// CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
3839
// CHECK-NOT: __riscv_xtheadba {{.*$}}
@@ -325,6 +326,14 @@
325326
// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVCP-EXT %s
326327
// CHECK-XSFVCP-EXT: __riscv_xsfvcp 1000000{{$}}
327328

329+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
330+
// RUN: -march=rv32ixsfvfwmaccqqq -x c -E -dM %s \
331+
// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVFWMACCQQQ-EXT %s
332+
// RUN: %clang --target=riscv64-unknown-linux-gnu \
333+
// RUN: -march=rv64ixsfvfwmaccqqq -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVFWMACCQQQ-EXT %s
335+
// CHECK-XSFVFWMACCQQQ-EXT: __riscv_xsfvfwmaccqqq 1000000{{$}}
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328337
// RUN: %clang --target=riscv32-unknown-linux-gnu \
329338
// RUN: -march=rv32ixsfvqmaccdod -x c -E -dM %s \
330339
// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVQMACCDOD-EXT %s

‎clang/test/Sema/rvv-required-features-invalid.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,3 +23,7 @@ void test_xsfvqmaccdod() {
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void test_xsfvqmaccqoq() {
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__riscv_sf_vqmacc_4x8x4(); // expected-error {{call to undeclared function '__riscv_sf_vqmacc_4x8x4'}}
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}
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void test_xsfvfwmaccqqq() {
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__riscv_sf_vfwmacc_4x4x4(); // expected-error {{call to undeclared function '__riscv_sf_vfwmacc_4x4x4'}}
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}

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