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hassnaaHamdihassnaaHamdi
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[SLP]: Add precommit test
Change-Id: Ibc0e74804e40ad7c17dffc4f217a25d94f832cfe
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‎llvm/test/Transforms/SLPVectorizer/infer-missing-instruction.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -passes=slp-vectorizer,instcombine -S < %s | FileCheck %s
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define dso_local noundef i32 @_Z4testiPs(i32 noundef %a, ptr noundef readonly captures(none) %b) local_unnamed_addr #0 {
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; CHECK-LABEL: define dso_local noundef i32 @_Z4testiPs(
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; CHECK-SAME: i32 noundef [[A:%.*]], ptr noundef readonly captures(none) [[B:%.*]]) local_unnamed_addr {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[SHR_1:%.*]] = lshr i32 [[A]], 1
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[A]], i64 0
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i32> [[TMP1]], <i32 2, i32 3>
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i64 0
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; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP5:%.*]] = lshr <4 x i32> [[TMP4]], <i32 4, i32 5, i32 6, i32 7>
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; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> poison, i32 [[A]], i64 0
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; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i32> [[TMP6]], <8 x i32> poison, <8 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP8:%.*]] = lshr <8 x i32> [[TMP7]], <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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; CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i32> poison, i32 [[A]], i64 0
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; CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x i32> [[TMP9]], i32 [[SHR_1]], i64 1
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; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
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; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <16 x i32> [[TMP10]], <16 x i32> [[TMP11]], <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
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; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
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; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <16 x i32> [[TMP12]], <16 x i32> [[TMP13]], <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 16, i32 17, i32 18, i32 19, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
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; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <16 x i32> [[TMP14]], <16 x i32> [[TMP15]], <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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; CHECK-NEXT: [[TMP17:%.*]] = and <16 x i32> [[TMP16]], splat (i32 16)
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; CHECK-NEXT: [[TMP18:%.*]] = load <16 x i16>, ptr [[B]], align 2
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; CHECK-NEXT: [[TMP19:%.*]] = sext <16 x i16> [[TMP18]] to <16 x i32>
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; CHECK-NEXT: [[TMP20:%.*]] = or <16 x i32> [[TMP17]], [[TMP19]]
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; CHECK-NEXT: [[TMP21:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP20]])
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; CHECK-NEXT: ret i32 [[TMP21]]
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;
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entry:
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%conv = and i32 %a, 16
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%0 = load i16, ptr %b, align 2
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%conv2 = sext i16 %0 to i32
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%or = or i32 %conv, %conv2
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%shr.1 = lshr i32 %a, 1
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%conv.1 = and i32 %shr.1, 16
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%arrayidx.1 = getelementptr inbounds nuw i8, ptr %b, i64 2
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%1 = load i16, ptr %arrayidx.1, align 2
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%conv2.1 = sext i16 %1 to i32
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%or.1 = or i32 %conv.1, %conv2.1
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%add.1 = add nsw i32 %or.1, %or
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%shr.2 = lshr i32 %a, 2
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%conv.2 = and i32 %shr.2, 16
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%arrayidx.2 = getelementptr inbounds nuw i8, ptr %b, i64 4
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%2 = load i16, ptr %arrayidx.2, align 2
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%conv2.2 = sext i16 %2 to i32
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%or.2 = or i32 %conv.2, %conv2.2
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%add.2 = add nsw i32 %or.2, %add.1
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%shr.3 = lshr i32 %a, 3
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%conv.3 = and i32 %shr.3, 16
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%arrayidx.3 = getelementptr inbounds nuw i8, ptr %b, i64 6
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%3 = load i16, ptr %arrayidx.3, align 2
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%conv2.3 = sext i16 %3 to i32
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%or.3 = or i32 %conv.3, %conv2.3
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%add.3 = add nsw i32 %or.3, %add.2
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%shr.4 = lshr i32 %a, 4
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%conv.4 = and i32 %shr.4, 16
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%arrayidx.4 = getelementptr inbounds nuw i8, ptr %b, i64 8
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%4 = load i16, ptr %arrayidx.4, align 2
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%conv2.4 = sext i16 %4 to i32
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%or.4 = or i32 %conv.4, %conv2.4
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%add.4 = add nsw i32 %or.4, %add.3
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%shr.5 = lshr i32 %a, 5
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%conv.5 = and i32 %shr.5, 16
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%arrayidx.5 = getelementptr inbounds nuw i8, ptr %b, i64 10
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%5 = load i16, ptr %arrayidx.5, align 2
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%conv2.5 = sext i16 %5 to i32
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%or.5 = or i32 %conv.5, %conv2.5
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%add.5 = add nsw i32 %or.5, %add.4
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%shr.6 = lshr i32 %a, 6
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%conv.6 = and i32 %shr.6, 16
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%arrayidx.6 = getelementptr inbounds nuw i8, ptr %b, i64 12
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%6 = load i16, ptr %arrayidx.6, align 2
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%conv2.6 = sext i16 %6 to i32
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%or.6 = or i32 %conv.6, %conv2.6
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%add.6 = add nsw i32 %or.6, %add.5
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%shr.7 = lshr i32 %a, 7
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%conv.7 = and i32 %shr.7, 16
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%arrayidx.7 = getelementptr inbounds nuw i8, ptr %b, i64 14
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%7 = load i16, ptr %arrayidx.7, align 2
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%conv2.7 = sext i16 %7 to i32
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%or.7 = or i32 %conv.7, %conv2.7
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%add.7 = add nsw i32 %or.7, %add.6
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%shr.8 = lshr i32 %a, 8
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%conv.8 = and i32 %shr.8, 16
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%arrayidx.8 = getelementptr inbounds nuw i8, ptr %b, i64 16
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%8 = load i16, ptr %arrayidx.8, align 2
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%conv2.8 = sext i16 %8 to i32
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%or.8 = or i32 %conv.8, %conv2.8
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%add.8 = add nsw i32 %or.8, %add.7
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%shr.9 = lshr i32 %a, 9
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%conv.9 = and i32 %shr.9, 16
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%arrayidx.9 = getelementptr inbounds nuw i8, ptr %b, i64 18
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%9 = load i16, ptr %arrayidx.9, align 2
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%conv2.9 = sext i16 %9 to i32
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%or.9 = or i32 %conv.9, %conv2.9
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%add.9 = add nsw i32 %or.9, %add.8
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%shr.10 = lshr i32 %a, 10
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%conv.10 = and i32 %shr.10, 16
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%arrayidx.10 = getelementptr inbounds nuw i8, ptr %b, i64 20
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%10 = load i16, ptr %arrayidx.10, align 2
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%conv2.10 = sext i16 %10 to i32
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%or.10 = or i32 %conv.10, %conv2.10
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%add.10 = add nsw i32 %or.10, %add.9
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%shr.11 = lshr i32 %a, 11
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%conv.11 = and i32 %shr.11, 16
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%arrayidx.11 = getelementptr inbounds nuw i8, ptr %b, i64 22
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%11 = load i16, ptr %arrayidx.11, align 2
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%conv2.11 = sext i16 %11 to i32
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%or.11 = or i32 %conv.11, %conv2.11
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%add.11 = add nsw i32 %or.11, %add.10
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%shr.12 = lshr i32 %a, 12
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%conv.12 = and i32 %shr.12, 16
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%arrayidx.12 = getelementptr inbounds nuw i8, ptr %b, i64 24
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%12 = load i16, ptr %arrayidx.12, align 2
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%conv2.12 = sext i16 %12 to i32
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%or.12 = or i32 %conv.12, %conv2.12
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%add.12 = add nsw i32 %or.12, %add.11
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%shr.13 = lshr i32 %a, 13
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%conv.13 = and i32 %shr.13, 16
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%arrayidx.13 = getelementptr inbounds nuw i8, ptr %b, i64 26
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%13 = load i16, ptr %arrayidx.13, align 2
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%conv2.13 = sext i16 %13 to i32
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%or.13 = or i32 %conv.13, %conv2.13
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%add.13 = add nsw i32 %or.13, %add.12
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%shr.14 = lshr i32 %a, 14
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%conv.14 = and i32 %shr.14, 16
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%arrayidx.14 = getelementptr inbounds nuw i8, ptr %b, i64 28
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%14 = load i16, ptr %arrayidx.14, align 2
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%conv2.14 = sext i16 %14 to i32
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%or.14 = or i32 %conv.14, %conv2.14
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%add.14 = add nsw i32 %or.14, %add.13
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%shr.15 = lshr i32 %a, 15
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%conv.15 = and i32 %shr.15, 16
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%arrayidx.15 = getelementptr inbounds nuw i8, ptr %b, i64 30
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%15 = load i16, ptr %arrayidx.15, align 2
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%conv2.15 = sext i16 %15 to i32
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%or.15 = or i32 %conv.15, %conv2.15
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%add.15 = add nsw i32 %or.15, %add.14
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ret i32 %add.15
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}

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