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nikicnikic
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[InstCombine] Infer zext nneg flag (#71534)
Use KnownBits to infer the nneg flag on zext instructions. Currently we only set nneg when converting sext -> zext, but don't set it when we have a zext in the first place. If we want to use it in optimizations, we should make sure the flag inference is consistent.
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+181
-176
lines changed

‎clang/test/Headers/wasm.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2183,7 +2183,7 @@ uint32_t test_i64x2_bitmask(v128_t a) {
21832183
// CHECK-NEXT: entry:
21842184
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <2 x i64>
21852185
// CHECK-NEXT: [[TMP1:%.*]] = and i32 [[B:%.*]], 63
2186-
// CHECK-NEXT: [[REM_I:%.*]] = zext i32 [[TMP1]] to i64
2186+
// CHECK-NEXT: [[REM_I:%.*]] = zext nneg i32 [[TMP1]] to i64
21872187
// CHECK-NEXT: [[SPLAT_SPLATINSERT_I:%.*]] = insertelement <2 x i64> poison, i64 [[REM_I]], i64 0
21882188
// CHECK-NEXT: [[SPLAT_SPLAT_I:%.*]] = shufflevector <2 x i64> [[SPLAT_SPLATINSERT_I]], <2 x i64> poison, <2 x i32> zeroinitializer
21892189
// CHECK-NEXT: [[SHL_I:%.*]] = shl <2 x i64> [[TMP0]], [[SPLAT_SPLAT_I]]
@@ -2198,7 +2198,7 @@ v128_t test_i64x2_shl(v128_t a, uint32_t b) {
21982198
// CHECK-NEXT: entry:
21992199
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <2 x i64>
22002200
// CHECK-NEXT: [[TMP1:%.*]] = and i32 [[B:%.*]], 63
2201-
// CHECK-NEXT: [[REM_I:%.*]] = zext i32 [[TMP1]] to i64
2201+
// CHECK-NEXT: [[REM_I:%.*]] = zext nneg i32 [[TMP1]] to i64
22022202
// CHECK-NEXT: [[SPLAT_SPLATINSERT_I:%.*]] = insertelement <2 x i64> poison, i64 [[REM_I]], i64 0
22032203
// CHECK-NEXT: [[SPLAT_SPLAT_I:%.*]] = shufflevector <2 x i64> [[SPLAT_SPLATINSERT_I]], <2 x i64> poison, <2 x i32> zeroinitializer
22042204
// CHECK-NEXT: [[SHR_I:%.*]] = ashr <2 x i64> [[TMP0]], [[SPLAT_SPLAT_I]]
@@ -2213,7 +2213,7 @@ v128_t test_i64x2_shr(v128_t a, uint32_t b) {
22132213
// CHECK-NEXT: entry:
22142214
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <2 x i64>
22152215
// CHECK-NEXT: [[TMP1:%.*]] = and i32 [[B:%.*]], 63
2216-
// CHECK-NEXT: [[REM_I:%.*]] = zext i32 [[TMP1]] to i64
2216+
// CHECK-NEXT: [[REM_I:%.*]] = zext nneg i32 [[TMP1]] to i64
22172217
// CHECK-NEXT: [[SPLAT_SPLATINSERT_I:%.*]] = insertelement <2 x i64> poison, i64 [[REM_I]], i64 0
22182218
// CHECK-NEXT: [[SPLAT_SPLAT_I:%.*]] = shufflevector <2 x i64> [[SPLAT_SPLATINSERT_I]], <2 x i64> poison, <2 x i32> zeroinitializer
22192219
// CHECK-NEXT: [[SHR_I:%.*]] = lshr <2 x i64> [[TMP0]], [[SPLAT_SPLAT_I]]

‎llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1221,6 +1221,11 @@ Instruction *InstCombinerImpl::visitZExt(ZExtInst &Zext) {
12211221
}
12221222
}
12231223

1224+
if (!Zext.hasNonNeg() && isKnownNonNegative(Src, DL, 0, &AC, &Zext, &DT)) {
1225+
Zext.setNonNeg();
1226+
return &Zext;
1227+
}
1228+
12241229
return nullptr;
12251230
}
12261231

‎llvm/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ define i32 @main(i32 %argc) {
88
; CHECK-NEXT: [[T3163:%.*]] = xor i8 [[T3151]], -1
99
; CHECK-NEXT: [[TMP1:%.*]] = shl i8 [[T3163]], 5
1010
; CHECK-NEXT: [[T4127:%.*]] = and i8 [[TMP1]], 64
11-
; CHECK-NEXT: [[T4086:%.*]] = zext i8 [[T4127]] to i32
11+
; CHECK-NEXT: [[T4086:%.*]] = zext nneg i8 [[T4127]] to i32
1212
; CHECK-NEXT: ret i32 [[T4086]]
1313
;
1414
%t3151 = trunc i32 %argc to i8

‎llvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2816,7 +2816,7 @@ define <8 x i32> @avx2_psrai_d_256_masked(<8 x i32> %v, i32 %a) {
28162816
define <8 x i64> @avx512_psrai_q_512_masked(<8 x i64> %v, i32 %a) {
28172817
; CHECK-LABEL: @avx512_psrai_q_512_masked(
28182818
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 63
2819-
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
2819+
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64
28202820
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[TMP2]], i64 0
28212821
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <8 x i64> [[DOTSPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
28222822
; CHECK-NEXT: [[TMP3:%.*]] = ashr <8 x i64> [[V:%.*]], [[DOTSPLAT]]
@@ -2843,7 +2843,7 @@ define <4 x i32> @sse2_psrli_d_128_masked(<4 x i32> %v, i32 %a) {
28432843
define <4 x i64> @avx2_psrli_q_256_masked(<4 x i64> %v, i32 %a) {
28442844
; CHECK-LABEL: @avx2_psrli_q_256_masked(
28452845
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 63
2846-
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
2846+
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64
28472847
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[TMP2]], i64 0
28482848
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i64> [[DOTSPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer
28492849
; CHECK-NEXT: [[TMP3:%.*]] = lshr <4 x i64> [[V:%.*]], [[DOTSPLAT]]
@@ -2871,7 +2871,7 @@ define <32 x i16> @avx512_psrli_w_512_masked(<32 x i16> %v, i32 %a) {
28712871
define <2 x i64> @sse2_pslli_q_128_masked(<2 x i64> %v, i32 %a) {
28722872
; CHECK-LABEL: @sse2_pslli_q_128_masked(
28732873
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 63
2874-
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
2874+
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64
28752875
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]], i64 0
28762876
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <2 x i64> [[DOTSPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
28772877
; CHECK-NEXT: [[TMP3:%.*]] = shl <2 x i64> [[V:%.*]], [[DOTSPLAT]]

‎llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2772,8 +2772,8 @@ define <2 x i64> @sse2_psll_q_128_masked_bitcast(<2 x i64> %v, <2 x i64> %a) {
27722772
; CHECK-NEXT: [[I:%.*]] = insertelement <4 x i32> [[M]], i32 0, i64 1
27732773
; CHECK-NEXT: [[SHAMT:%.*]] = bitcast <4 x i32> [[I]] to <2 x i64>
27742774
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[SHAMT]], <2 x i64> poison, <2 x i32> zeroinitializer
2775-
; CHECK-NEXT: [[TMP2:%.*]] = shl <2 x i64> [[V:%.*]], [[TMP1]]
2776-
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
2775+
; CHECK-NEXT: [[R:%.*]] = shl <2 x i64> [[V:%.*]], [[TMP1]]
2776+
; CHECK-NEXT: ret <2 x i64> [[R]]
27772777
;
27782778
%b = bitcast <2 x i64> %a to <4 x i32>
27792779
%m = and <4 x i32> %b, <i32 31, i32 poison, i32 poison, i32 poison>
@@ -2856,7 +2856,7 @@ define <8 x i32> @avx2_psrai_d_256_masked(<8 x i32> %v, i32 %a) {
28562856
define <8 x i64> @avx512_psrai_q_512_masked(<8 x i64> %v, i32 %a) {
28572857
; CHECK-LABEL: @avx512_psrai_q_512_masked(
28582858
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 63
2859-
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
2859+
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64
28602860
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[TMP2]], i64 0
28612861
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <8 x i64> [[DOTSPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
28622862
; CHECK-NEXT: [[TMP3:%.*]] = ashr <8 x i64> [[V:%.*]], [[DOTSPLAT]]
@@ -2883,7 +2883,7 @@ define <4 x i32> @sse2_psrli_d_128_masked(<4 x i32> %v, i32 %a) {
28832883
define <4 x i64> @avx2_psrli_q_256_masked(<4 x i64> %v, i32 %a) {
28842884
; CHECK-LABEL: @avx2_psrli_q_256_masked(
28852885
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 63
2886-
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
2886+
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64
28872887
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[TMP2]], i64 0
28882888
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i64> [[DOTSPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer
28892889
; CHECK-NEXT: [[TMP3:%.*]] = lshr <4 x i64> [[V:%.*]], [[DOTSPLAT]]
@@ -2911,7 +2911,7 @@ define <32 x i16> @avx512_psrli_w_512_masked(<32 x i16> %v, i32 %a) {
29112911
define <2 x i64> @sse2_pslli_q_128_masked(<2 x i64> %v, i32 %a) {
29122912
; CHECK-LABEL: @sse2_pslli_q_128_masked(
29132913
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 63
2914-
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
2914+
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64
29152915
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]], i64 0
29162916
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <2 x i64> [[DOTSPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
29172917
; CHECK-NEXT: [[TMP3:%.*]] = shl <2 x i64> [[V:%.*]], [[DOTSPLAT]]

‎llvm/test/Transforms/InstCombine/adjust-for-minmax.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -414,7 +414,7 @@ define <2 x i64> @umax_zext_vec(<2 x i32> %a) {
414414
define i64 @umin_zext(i32 %a) {
415415
; CHECK-LABEL: @umin_zext(
416416
; CHECK-NEXT: [[NARROW:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 2)
417-
; CHECK-NEXT: [[MIN:%.*]] = zext i32 [[NARROW]] to i64
417+
; CHECK-NEXT: [[MIN:%.*]] = zext nneg i32 [[NARROW]] to i64
418418
; CHECK-NEXT: ret i64 [[MIN]]
419419
;
420420
%a_ext = zext i32 %a to i64
@@ -426,7 +426,7 @@ define i64 @umin_zext(i32 %a) {
426426
define <2 x i64> @umin_zext_vec(<2 x i32> %a) {
427427
; CHECK-LABEL: @umin_zext_vec(
428428
; CHECK-NEXT: [[NARROW:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 2, i32 2>)
429-
; CHECK-NEXT: [[MIN:%.*]] = zext <2 x i32> [[NARROW]] to <2 x i64>
429+
; CHECK-NEXT: [[MIN:%.*]] = zext nneg <2 x i32> [[NARROW]] to <2 x i64>
430430
; CHECK-NEXT: ret <2 x i64> [[MIN]]
431431
;
432432
%a_ext = zext <2 x i32> %a to <2 x i64>

‎llvm/test/Transforms/InstCombine/and-narrow.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ define i16 @zext_lshr(i8 %x) {
4747
; CHECK-LABEL: @zext_lshr(
4848
; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 [[X:%.*]], 4
4949
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]]
50-
; CHECK-NEXT: [[R:%.*]] = zext i8 [[TMP2]] to i16
50+
; CHECK-NEXT: [[R:%.*]] = zext nneg i8 [[TMP2]] to i16
5151
; CHECK-NEXT: ret i16 [[R]]
5252
;
5353
%z = zext i8 %x to i16
@@ -60,7 +60,7 @@ define i16 @zext_ashr(i8 %x) {
6060
; CHECK-LABEL: @zext_ashr(
6161
; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 [[X:%.*]], 2
6262
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]]
63-
; CHECK-NEXT: [[R:%.*]] = zext i8 [[TMP2]] to i16
63+
; CHECK-NEXT: [[R:%.*]] = zext nneg i8 [[TMP2]] to i16
6464
; CHECK-NEXT: ret i16 [[R]]
6565
;
6666
%z = zext i8 %x to i16
@@ -125,7 +125,7 @@ define <2 x i16> @zext_lshr_vec(<2 x i8> %x) {
125125
; CHECK-LABEL: @zext_lshr_vec(
126126
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 4, i8 2>
127127
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i8> [[TMP1]], [[X]]
128-
; CHECK-NEXT: [[R:%.*]] = zext <2 x i8> [[TMP2]] to <2 x i16>
128+
; CHECK-NEXT: [[R:%.*]] = zext nneg <2 x i8> [[TMP2]] to <2 x i16>
129129
; CHECK-NEXT: ret <2 x i16> [[R]]
130130
;
131131
%z = zext <2 x i8> %x to <2 x i16>
@@ -138,7 +138,7 @@ define <2 x i16> @zext_ashr_vec(<2 x i8> %x) {
138138
; CHECK-LABEL: @zext_ashr_vec(
139139
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 2, i8 3>
140140
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i8> [[TMP1]], [[X]]
141-
; CHECK-NEXT: [[R:%.*]] = zext <2 x i8> [[TMP2]] to <2 x i16>
141+
; CHECK-NEXT: [[R:%.*]] = zext nneg <2 x i8> [[TMP2]] to <2 x i16>
142142
; CHECK-NEXT: ret <2 x i16> [[R]]
143143
;
144144
%z = zext <2 x i8> %x to <2 x i16>

‎llvm/test/Transforms/InstCombine/and-xor-or.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4207,7 +4207,7 @@ define i16 @and_zext_zext(i8 %x, i4 %y) {
42074207
; CHECK-SAME: (i8 [[X:%.*]], i4 [[Y:%.*]]) {
42084208
; CHECK-NEXT: [[TMP1:%.*]] = zext i4 [[Y]] to i8
42094209
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]]
4210-
; CHECK-NEXT: [[R:%.*]] = zext i8 [[TMP2]] to i16
4210+
; CHECK-NEXT: [[R:%.*]] = zext nneg i8 [[TMP2]] to i16
42114211
; CHECK-NEXT: ret i16 [[R]]
42124212
;
42134213
%zx = zext i8 %x to i16

‎llvm/test/Transforms/InstCombine/and.ll

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -525,7 +525,7 @@ define <2 x i32> @and_demanded_bits_splat_vec(<2 x i32> %x) {
525525
define i32 @and_zext_demanded(i16 %x, i32 %y) {
526526
; CHECK-LABEL: @and_zext_demanded(
527527
; CHECK-NEXT: [[S:%.*]] = lshr i16 [[X:%.*]], 8
528-
; CHECK-NEXT: [[Z:%.*]] = zext i16 [[S]] to i32
528+
; CHECK-NEXT: [[Z:%.*]] = zext nneg i16 [[S]] to i32
529529
; CHECK-NEXT: ret i32 [[Z]]
530530
;
531531
%s = lshr i16 %x, 8
@@ -618,7 +618,7 @@ define i64 @test35(i32 %X) {
618618
; CHECK-LABEL: @test35(
619619
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[X:%.*]]
620620
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 240
621-
; CHECK-NEXT: [[RES:%.*]] = zext i32 [[TMP2]] to i64
621+
; CHECK-NEXT: [[RES:%.*]] = zext nneg i32 [[TMP2]] to i64
622622
; CHECK-NEXT: ret i64 [[RES]]
623623
;
624624
%zext = zext i32 %X to i64
@@ -631,7 +631,7 @@ define <2 x i64> @test35_uniform(<2 x i32> %X) {
631631
; CHECK-LABEL: @test35_uniform(
632632
; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i32> zeroinitializer, [[X:%.*]]
633633
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 240, i32 240>
634-
; CHECK-NEXT: [[RES:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64>
634+
; CHECK-NEXT: [[RES:%.*]] = zext nneg <2 x i32> [[TMP2]] to <2 x i64>
635635
; CHECK-NEXT: ret <2 x i64> [[RES]]
636636
;
637637
%zext = zext <2 x i32> %X to <2 x i64>
@@ -644,7 +644,7 @@ define i64 @test36(i32 %X) {
644644
; CHECK-LABEL: @test36(
645645
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 7
646646
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 240
647-
; CHECK-NEXT: [[RES:%.*]] = zext i32 [[TMP2]] to i64
647+
; CHECK-NEXT: [[RES:%.*]] = zext nneg i32 [[TMP2]] to i64
648648
; CHECK-NEXT: ret i64 [[RES]]
649649
;
650650
%zext = zext i32 %X to i64
@@ -657,7 +657,7 @@ define <2 x i64> @test36_uniform(<2 x i32> %X) {
657657
; CHECK-LABEL: @test36_uniform(
658658
; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 7, i32 7>
659659
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 240, i32 240>
660-
; CHECK-NEXT: [[RES:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64>
660+
; CHECK-NEXT: [[RES:%.*]] = zext nneg <2 x i32> [[TMP2]] to <2 x i64>
661661
; CHECK-NEXT: ret <2 x i64> [[RES]]
662662
;
663663
%zext = zext <2 x i32> %X to <2 x i64>
@@ -683,7 +683,7 @@ define i64 @test37(i32 %X) {
683683
; CHECK-LABEL: @test37(
684684
; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[X:%.*]], 7
685685
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 240
686-
; CHECK-NEXT: [[RES:%.*]] = zext i32 [[TMP2]] to i64
686+
; CHECK-NEXT: [[RES:%.*]] = zext nneg i32 [[TMP2]] to i64
687687
; CHECK-NEXT: ret i64 [[RES]]
688688
;
689689
%zext = zext i32 %X to i64
@@ -696,7 +696,7 @@ define <2 x i64> @test37_uniform(<2 x i32> %X) {
696696
; CHECK-LABEL: @test37_uniform(
697697
; CHECK-NEXT: [[TMP1:%.*]] = mul <2 x i32> [[X:%.*]], <i32 7, i32 7>
698698
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 240, i32 240>
699-
; CHECK-NEXT: [[RES:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64>
699+
; CHECK-NEXT: [[RES:%.*]] = zext nneg <2 x i32> [[TMP2]] to <2 x i64>
700700
; CHECK-NEXT: ret <2 x i64> [[RES]]
701701
;
702702
%zext = zext <2 x i32> %X to <2 x i64>
@@ -721,7 +721,7 @@ define <2 x i64> @test37_nonuniform(<2 x i32> %X) {
721721
define i64 @test38(i32 %X) {
722722
; CHECK-LABEL: @test38(
723723
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 240
724-
; CHECK-NEXT: [[RES:%.*]] = zext i32 [[TMP1]] to i64
724+
; CHECK-NEXT: [[RES:%.*]] = zext nneg i32 [[TMP1]] to i64
725725
; CHECK-NEXT: ret i64 [[RES]]
726726
;
727727
%zext = zext i32 %X to i64
@@ -733,7 +733,7 @@ define i64 @test38(i32 %X) {
733733
define i64 @test39(i32 %X) {
734734
; CHECK-LABEL: @test39(
735735
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 240
736-
; CHECK-NEXT: [[RES:%.*]] = zext i32 [[TMP1]] to i64
736+
; CHECK-NEXT: [[RES:%.*]] = zext nneg i32 [[TMP1]] to i64
737737
; CHECK-NEXT: ret i64 [[RES]]
738738
;
739739
%zext = zext i32 %X to i64

‎llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ define <2 x i32> @OrZextOrVec(<2 x i2> %a) {
5454
define i5 @AndZextAnd(i3 %a) {
5555
; CHECK-LABEL: @AndZextAnd(
5656
; CHECK-NEXT: [[TMP1:%.*]] = and i3 [[A:%.*]], 2
57-
; CHECK-NEXT: [[OP2:%.*]] = zext i3 [[TMP1]] to i5
57+
; CHECK-NEXT: [[OP2:%.*]] = zext nneg i3 [[TMP1]] to i5
5858
; CHECK-NEXT: ret i5 [[OP2]]
5959
;
6060
%op1 = and i3 %a, 3
@@ -66,7 +66,7 @@ define i5 @AndZextAnd(i3 %a) {
6666
define <2 x i32> @AndZextAndVec(<2 x i8> %a) {
6767
; CHECK-LABEL: @AndZextAndVec(
6868
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[A:%.*]], <i8 5, i8 0>
69-
; CHECK-NEXT: [[OP2:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>
69+
; CHECK-NEXT: [[OP2:%.*]] = zext nneg <2 x i8> [[TMP1]] to <2 x i32>
7070
; CHECK-NEXT: ret <2 x i32> [[OP2]]
7171
;
7272
%op1 = and <2 x i8> %a, <i8 7, i8 0>

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