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[AArch64] Remove post-decoding instruction mutations
These instructions can now be fully decoded automatically.
1 parent c256966 commit 55d5172

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5 files changed

+107
-39
lines changed

5 files changed

+107
-39
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 18 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1561,13 +1561,12 @@ def VectorIndexHOperand : AsmVectorIndex<0, 7>;
15611561
def VectorIndexSOperand : AsmVectorIndex<0, 3>;
15621562
def VectorIndexDOperand : AsmVectorIndex<0, 1>;
15631563

1564-
let OperandNamespace = "AArch64" in {
1565-
let OperandType = "OPERAND_IMPLICIT_IMM_0" in {
1566-
defm VectorIndex0 : VectorIndex<i64, VectorIndex0Operand,
1567-
[{ return ((uint64_t)Imm) == 0; }]>;
1568-
defm VectorIndex032b : VectorIndex<i32, VectorIndex0Operand,
1569-
[{ return ((uint32_t)Imm) == 0; }]>;
1570-
}
1564+
let OperandNamespace = "AArch64", OperandType = "OPERAND_IMPLICIT_IMM_0",
1565+
DecoderMethod = "DecodeZeroImm" in {
1566+
defm VectorIndex0 : VectorIndex<i64, VectorIndex0Operand,
1567+
[{ return ((uint64_t)Imm) == 0; }]>;
1568+
defm VectorIndex032b : VectorIndex<i32, VectorIndex0Operand,
1569+
[{ return ((uint32_t)Imm) == 0; }]>;
15711570
}
15721571
defm VectorIndex1 : VectorIndex<i64, VectorIndex1Operand,
15731572
[{ return ((uint64_t)Imm) == 1; }]>;
@@ -1620,6 +1619,7 @@ def sme_elm_idx0_0 : Operand<i32>, TImmLeaf<i32, [{
16201619
let PrintMethod = "printMatrixIndex";
16211620
let OperandNamespace = "AArch64";
16221621
let OperandType = "OPERAND_IMPLICIT_IMM_0";
1622+
let DecoderMethod = "DecodeZeroImm";
16231623
}
16241624
def sme_elm_idx0_1 : Operand<i32>, TImmLeaf<i32, [{
16251625
return ((uint32_t)Imm) <= 1;
@@ -1683,6 +1683,7 @@ def uimm0s2range : Operand<i64>, ImmLeaf<i64,
16831683
let ParserMatchClass = UImm0s2RangeOperand;
16841684
let OperandNamespace = "AArch64";
16851685
let OperandType = "OPERAND_IMPLICIT_IMM_0";
1686+
let DecoderMethod = "DecodeZeroImm";
16861687
}
16871688

16881689
def uimm0s4range : Operand<i64>, ImmLeaf<i64,
@@ -1691,6 +1692,7 @@ def uimm0s4range : Operand<i64>, ImmLeaf<i64,
16911692
let ParserMatchClass = UImm0s4RangeOperand;
16921693
let OperandNamespace = "AArch64";
16931694
let OperandType = "OPERAND_IMPLICIT_IMM_0";
1695+
let DecoderMethod = "DecodeZeroImm";
16941696
}
16951697

16961698
def uimm1s2range : Operand<i64>, ImmLeaf<i64,
@@ -8220,18 +8222,23 @@ multiclass SMov {
82208222
// streaming mode.
82218223
let Predicates = [HasNEONandIsStreamingSafe] in {
82228224
def vi8to32_idx0 : SIMDSMov<0, ".b", GPR32, VectorIndex0> {
8225+
bits<0> idx;
82238226
let Inst{20-16} = 0b00001;
82248227
}
82258228
def vi8to64_idx0 : SIMDSMov<1, ".b", GPR64, VectorIndex0> {
8229+
bits<0> idx;
82268230
let Inst{20-16} = 0b00001;
82278231
}
82288232
def vi16to32_idx0 : SIMDSMov<0, ".h", GPR32, VectorIndex0> {
8233+
bits<0> idx;
82298234
let Inst{20-16} = 0b00010;
82308235
}
82318236
def vi16to64_idx0 : SIMDSMov<1, ".h", GPR64, VectorIndex0> {
8237+
bits<0> idx;
82328238
let Inst{20-16} = 0b00010;
82338239
}
82348240
def vi32to64_idx0 : SIMDSMov<1, ".s", GPR64, VectorIndex0> {
8241+
bits<0> idx;
82358242
let Inst{20-16} = 0b00100;
82368243
}
82378244
}
@@ -8267,15 +8274,19 @@ multiclass UMov {
82678274
// streaming mode.
82688275
let Predicates = [HasNEONandIsStreamingSafe] in {
82698276
def vi8_idx0 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndex0> {
8277+
bits<0> idx;
82708278
let Inst{20-16} = 0b00001;
82718279
}
82728280
def vi16_idx0 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndex0> {
8281+
bits<0> idx;
82738282
let Inst{20-16} = 0b00010;
82748283
}
82758284
def vi32_idx0 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndex0> {
8285+
bits<0> idx;
82768286
let Inst{20-16} = 0b00100;
82778287
}
82788288
def vi64_idx0 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndex0> {
8289+
bits<0> idx;
82798290
let Inst{20-16} = 0b01000;
82808291
}
82818292
def : SIMDMovAlias<"mov", ".s",

‎llvm/lib/Target/AArch64/CMakeLists.txt‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,7 @@ tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
77
tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
88
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
99
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
10-
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
11-
-ignore-non-decodable-operands)
10+
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
1211
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
1312
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
1413
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner

‎llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp‎

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,18 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
130130
return Success;
131131
}
132132

133+
static DecodeStatus DecodeMPRRegisterClass(MCInst &Inst,
134+
const MCDisassembler *Decoder) {
135+
Inst.addOperand(MCOperand::createReg(AArch64::ZA));
136+
return Success;
137+
}
138+
139+
static DecodeStatus DecodeZTRRegisterClass(MCInst &Inst,
140+
const MCDisassembler *Decoder) {
141+
Inst.addOperand(MCOperand::createReg(AArch64::ZT0));
142+
return Success;
143+
}
144+
133145
static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
134146
{AArch64::ZAB0},
135147
{AArch64::ZAH0, AArch64::ZAH1},
@@ -141,10 +153,19 @@ static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
141153
AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
142154
AArch64::ZAQ14, AArch64::ZAQ15}};
143155

156+
template <unsigned NumBitsForTile>
157+
static DecodeStatus DecodeMatrixTile(MCInst &Inst,
158+
const MCDisassembler *Decoder) {
159+
static_assert(NumBitsForTile == 0);
160+
Inst.addOperand(MCOperand::createReg(AArch64::ZAB0));
161+
return Success;
162+
}
163+
144164
template <unsigned NumBitsForTile>
145165
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
146166
uint64_t Address,
147167
const MCDisassembler *Decoder) {
168+
static_assert(NumBitsForTile != 0);
148169
unsigned LastReg = (1 << NumBitsForTile) - 1;
149170
if (RegNo > LastReg)
150171
return Fail;
@@ -1392,6 +1413,11 @@ DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
13921413
return Success;
13931414
}
13941415

1416+
static DecodeStatus DecodeZeroImm(MCInst &Inst, const MCDisassembler *Decoder) {
1417+
Inst.addOperand(MCOperand::createImm(0));
1418+
return Success;
1419+
}
1420+
13951421
template <int Bits>
13961422
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
13971423
const MCDisassembler *Decoder) {
@@ -1540,6 +1566,7 @@ DecodeSMESpillFillInstruction(MCInst &Inst, uint32_t Bits, uint64_t Addr,
15401566
unsigned RnBits = fieldFromInstruction(Bits, 5, 5);
15411567
unsigned Imm4Bits = fieldFromInstruction(Bits, 0, 4);
15421568

1569+
DecodeMPRRegisterClass(Inst, Decoder);
15431570
DecodeSimpleRegisterClass<AArch64::MatrixIndexGPR32_12_15RegClassID, 0, 4>(
15441571
Inst, RvBits, Addr, Decoder);
15451572
Inst.addOperand(MCOperand::createImm(Imm4Bits));
@@ -1583,33 +1610,6 @@ DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
15831610
for (const auto *Table : Tables) {
15841611
DecodeStatus Result =
15851612
decodeInstruction(Table, MI, Insn, Address, this, STI);
1586-
1587-
const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
1588-
1589-
// For Scalable Matrix Extension (SME) instructions that have an implicit
1590-
// operand for the accumulator (ZA) or implicit immediate zero which isn't
1591-
// encoded, manually insert operand.
1592-
for (unsigned i = 0; i < Desc.getNumOperands(); i++) {
1593-
if (Desc.operands()[i].OperandType == MCOI::OPERAND_REGISTER) {
1594-
switch (Desc.operands()[i].RegClass) {
1595-
default:
1596-
break;
1597-
case AArch64::MPRRegClassID:
1598-
MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA));
1599-
break;
1600-
case AArch64::MPR8RegClassID:
1601-
MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0));
1602-
break;
1603-
case AArch64::ZTRRegClassID:
1604-
MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0));
1605-
break;
1606-
}
1607-
} else if (Desc.operands()[i].OperandType ==
1608-
AArch64::OPERAND_IMPLICIT_IMM_0) {
1609-
MI.insert(MI.begin() + i, MCOperand::createImm(0));
1610-
}
1611-
}
1612-
16131613
if (Result != MCDisassembler::Fail)
16141614
return Result;
16151615
}

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