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[PowerPC] Implement Context Switch Instr mtlpl
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llvm/lib/Target/PowerPC/PPCInstrFuture.td

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@@ -194,6 +194,22 @@ class XX3Form_XTAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
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let Inst{31} = XT{5};
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}
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class XForm_RBS5<bits<6> opCode, bits<10> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opCode, OOL, IOL, asmstr, itin> {
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bits<5> RB;
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bits<5> RS;
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let Pattern = pattern;
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let Inst{6...10} = RS;
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let Inst{11...15} = 0;
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let Inst{16...20} = RB;
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let Inst{21...30} = xo;
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let Inst{31} = 0;
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}
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class XX3Form_XTAB6_S<bits<5> xo, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: I<59, OOL, IOL, asmstr, NoItinerary> {
@@ -323,6 +339,11 @@ let Predicates = [IsISAFuture] in {
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(ins g8rc:$RB, g8rc:$RS, u2imm:$RIC,
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u1imm:$PRS, u1imm:$R),
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"tlbiep $RB, $RS, $RIC, $PRS, $R", []>;
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def MTLPL : XForm_RBS5<31, 275, (outs), (ins gprc:$RB, gprc:$RS),
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"mtlpl $RB, $RS", IIC_SprMTSPR, []>;
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let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
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def MTLPL8 : XForm_RBS5<31, 275, (outs), (ins g8rc:$RB, g8rc:$RS),
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"mtlpl $RB, $RS", IIC_SprMTSPR, []>, isPPC64;
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}
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}
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llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt

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@@ -286,6 +286,9 @@
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#CHECK: xvmulhuh 4, 5, 7
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0xf0,0x85,0x3b,0xd0
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#CHECK: mtlpl 3, 4
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0x7c,0x80,0x1a,0x26
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#CHECK: xxmulmul 8, 3, 4, 2
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0xed,0x03,0x22,0x08
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llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt

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@@ -280,6 +280,9 @@
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#CHECK: xvmulhuh 4, 5, 7
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0xd0,0x3b,0x85,0xf0
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#CHECK: mtlpl 3, 4
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0x26,0x1a,0x80,0x7c
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#CHECK: xxmulmul 8, 3, 4, 2
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0x08,0x22,0x03,0xed
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llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s

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@@ -403,6 +403,10 @@
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#CHECK-BE: xvmulhuh 4, 5, 7 # encoding: [0xf0,0x85,0x3b,0xd0]
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#CHECK-LE: xvmulhuh 4, 5, 7 # encoding: [0xd0,0x3b,0x85,0xf0]
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mtlpl 3, 4
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#CHECK-BE: mtlpl 3, 4 # encoding: [0x7c,0x80,0x1a,0x26]
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#CHECK-LE: mtlpl 3, 4 # encoding: [0x26,0x1a,0x80,0x7c]
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xxmulmul 8, 3, 4, 2
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#CHECK-BE: xxmulmul 8, 3, 4, 2 # encoding: [0xed,0x03,0x22,0x08]
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#CHECK-LE: xxmulmul 8, 3, 4, 2 # encoding: [0x08,0x22,0x03,0xed]

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