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[ELF][ARM] Fix regression of BL->BLX substitution after D73542
D73542 made a typo (`rel.type == R_PLT_PC`; should be `rel.expr`) and introduced a regression: BL->BLX substitution was disabled when the target symbol is preemptible (expr is R_PLT_PC). The two added bl instructions in arm-thumb-interwork-shared.s check that we patch BL to BLX. Fixes https://bugs.chromium.org/p/chromium/issues/detail?id=1047531
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-29
lines changed

2 files changed

+34
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lines changed

‎lld/ELF/Arch/ARM.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -409,7 +409,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
409409
// not of type STT_FUNC then we must preserve the original instruction.
410410
// PLT entries are always ARM state so we know we don't need to interwork.
411411
bool isBlx = (read32le(loc) & 0xfe000000) == 0xfa000000;
412-
bool interwork = rel.sym && rel.sym->isFunc() && rel.type != R_PLT_PC;
412+
bool interwork = rel.sym && rel.sym->isFunc() && rel.expr != R_PLT_PC;
413413
if (interwork ? val & 1 : isBlx) {
414414
// The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
415415
checkInt(loc, val, 26, rel);
@@ -454,7 +454,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
454454
// not of type STT_FUNC then we must preserve the original instruction.
455455
// PLT entries are always ARM state so we know we need to interwork.
456456
bool isBlx = (read16le(loc + 2) & 0x1000) == 0;
457-
bool interwork = (rel.sym && rel.sym->isFunc()) || rel.type == R_PLT_PC;
457+
bool interwork = (rel.sym && rel.sym->isFunc()) || rel.expr == R_PLT_PC;
458458
if (interwork ? (val & 1) == 0 : isBlx) {
459459
// We are writing a BLX. Ensure BLX destination is 4-byte aligned. As
460460
// the BLX instruction may only be two byte aligned. This must be done

‎lld/test/ELF/arm-thumb-interwork-shared.s‎

Lines changed: 32 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// REQUIRES: arm
22
// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t
33
// RUN: ld.lld %t --shared -o %t.so
4-
// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t.so | FileCheck %s
4+
// RUN: llvm-objdump -d --no-show-raw-insn -triple=thumbv7a-none-linux-gnueabi %t.so | FileCheck %s
55
.syntax unified
66
.global sym1
77
.global elsewhere
@@ -10,46 +10,51 @@ sym1:
1010
b.w elsewhere
1111
b.w weakref
1212

13+
bl elsewhere
14+
bl weakref
15+
1316
// Check that we generate a thunk for an undefined symbol called via a plt
1417
// entry.
1518

1619
// CHECK: Disassembly of section .text:
1720
// CHECK-EMPTY:
1821
// CHECK-NEXT: sym1:
19-
// CHECK-NEXT: 11e0: 00 f0 02 b8 b.w #4 <__ThumbV7PILongThunk_elsewhere>
20-
// CHECK-NEXT: 11e4: 00 f0 06 b8 b.w #12 <__ThumbV7PILongThunk_weakref>
22+
// CHECK-NEXT: 11e0: b.w #12 <__ThumbV7PILongThunk_elsewhere>
23+
// CHECK-NEXT: b.w #20 <__ThumbV7PILongThunk_weakref>
24+
// CHECK-NEXT: blx #68
25+
// CHECK-NEXT: blx #80
2126
// CHECK: __ThumbV7PILongThunk_elsewhere:
22-
// CHECK-NEXT: 11e8: 40 f2 2c 0c movw r12, #44
23-
// CHECK-NEXT: 11ec: c0 f2 00 0c movt r12, #0
24-
// CHECK-NEXT: 11f0: fc 44 add r12, pc
25-
// CHECK-NEXT: 11f2: 60 47 bx r12
27+
// CHECK-NEXT: 11f0: movw r12, #52
28+
// CHECK-NEXT: movt r12, #0
29+
// CHECK-NEXT: add r12, pc
30+
// CHECK-NEXT: bx r12
2631
// CHECK: __ThumbV7PILongThunk_weakref:
27-
// CHECK-NEXT: 11f4: 40 f2 30 0c movw r12, #48
28-
// CHECK-NEXT: 11f8: c0 f2 00 0c movt r12, #0
29-
// CHECK-NEXT: 11fc: fc 44 add r12, pc
30-
// CHECK-NEXT: 11fe: 60 47 bx r12
32+
// CHECK-NEXT: 11fc: movw r12, #56
33+
// CHECK-NEXT: movt r12, #0
34+
// CHECK-NEXT: add r12, pc
35+
// CHECK-NEXT: bx r12
3136

3237
// CHECK: Disassembly of section .plt:
3338
// CHECK-EMPTY:
3439
// CHECK-NEXT: $a:
35-
// CHECK-NEXT: 1200: 04 e0 2d e5 str lr, [sp, #-4]!
36-
// CHECK-NEXT: 1204: 00 e6 8f e2 add lr, pc, #0, #12
37-
// CHECK-NEXT: 1208: 02 ea 8e e2 add lr, lr, #8192
38-
// CHECK-NEXT: 120c: 94 f0 be e5 ldr pc, [lr, #148]!
40+
// CHECK-NEXT: 1210: str lr, [sp, #-4]!
41+
// CHECK-NEXT: add lr, pc, #0, #12
42+
// CHECK-NEXT: add lr, lr, #8192
43+
// CHECK-NEXT: ldr pc, [lr, #148]!
3944
// CHECK: $d:
40-
// CHECK-NEXT: 1210: d4 d4 d4 d4 .word 0xd4d4d4d4
41-
// CHECK-NEXT: 1214: d4 d4 d4 d4 .word 0xd4d4d4d4
42-
// CHECK-NEXT: 1218: d4 d4 d4 d4 .word 0xd4d4d4d4
43-
// CHECK-NEXT: 121c: d4 d4 d4 d4 .word 0xd4d4d4d4
45+
// CHECK-NEXT: 1220: d4 d4 d4 d4 .word 0xd4d4d4d4
46+
// CHECK-NEXT: .word 0xd4d4d4d4
47+
// CHECK-NEXT: .word 0xd4d4d4d4
48+
// CHECK-NEXT: .word 0xd4d4d4d4
4449
// CHECK: $a:
45-
// CHECK-NEXT: 1220: 00 c6 8f e2 add r12, pc, #0, #12
46-
// CHECK-NEXT: 1224: 02 ca 8c e2 add r12, r12, #8192
47-
// CHECK-NEXT: 1228: 7c f0 bc e5 ldr pc, [r12, #124]!
50+
// CHECK-NEXT: 1230: add r12, pc, #0, #12
51+
// CHECK-NEXT: add r12, r12, #8192
52+
// CHECK-NEXT: ldr pc, [r12, #124]!
4853
// CHECK: $d:
49-
// CHECK-NEXT: 122c: d4 d4 d4 d4 .word 0xd4d4d4d4
54+
// CHECK-NEXT: 123c: d4 d4 d4 d4 .word 0xd4d4d4d4
5055
// CHECK: $a:
51-
// CHECK-NEXT: 1230: 00 c6 8f e2 add r12, pc, #0, #12
52-
// CHECK-NEXT: 1234: 02 ca 8c e2 add r12, r12, #8192
53-
// CHECK-NEXT: 1238: 70 f0 bc e5 ldr pc, [r12, #112]!
56+
// CHECK-NEXT: 1240: add r12, pc, #0, #12
57+
// CHECK-NEXT: add r12, r12, #8192
58+
// CHECK-NEXT: ldr pc, [r12, #112]!
5459
// CHECK: $d:
55-
// CHECK-NEXT: 123c: d4 d4 d4 d4 .word 0xd4d4d4d4
60+
// CHECK-NEXT: 124c: d4 d4 d4 d4 .word 0xd4d4d4d4

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