@@ -201,7 +201,7 @@ class X86AsmBackend : public MCAsmBackend {
201201 bool padInstructionEncoding (MCRelaxableFragment &RF, MCCodeEmitter &Emitter,
202202 unsigned &RemainingSize) const ;
203203
204- bool finishLayout (const MCAssembler &Asm) const override ;
204+ void finishLayout (const MCAssembler &Asm) const override ;
205205
206206 unsigned getMaximumNopSize (const MCSubtargetInfo &STI) const override ;
207207
@@ -854,15 +854,15 @@ bool X86AsmBackend::padInstructionEncoding(MCRelaxableFragment &RF,
854854 return Changed;
855855}
856856
857- bool X86AsmBackend::finishLayout (const MCAssembler &Asm) const {
857+ void X86AsmBackend::finishLayout (MCAssembler const &Asm) const {
858858 // See if we can further relax some instructions to cut down on the number of
859859 // nop bytes required for code alignment. The actual win is in reducing
860860 // instruction count, not number of bytes. Modern X86-64 can easily end up
861861 // decode limited. It is often better to reduce the number of instructions
862862 // (i.e. eliminate nops) even at the cost of increasing the size and
863863 // complexity of others.
864864 if (!X86PadForAlign && !X86PadForBranchAlign)
865- return false ;
865+ return ;
866866
867867 // The processed regions are delimitered by LabeledFragments. -g may have more
868868 // MCSymbols and therefore different relaxation results. X86PadForAlign is
@@ -907,6 +907,9 @@ bool X86AsmBackend::finishLayout(const MCAssembler &Asm) const {
907907 continue ;
908908 }
909909
910+ #ifndef NDEBUG
911+ const uint64_t OrigOffset = Asm.getFragmentOffset (F);
912+ #endif
910913 const uint64_t OrigSize = Asm.computeFragmentSize (F);
911914
912915 // To keep the effects local, prefer to relax instructions closest to
@@ -919,7 +922,8 @@ bool X86AsmBackend::finishLayout(const MCAssembler &Asm) const {
919922 // Give the backend a chance to play any tricks it wishes to increase
920923 // the encoding size of the given instruction. Target independent code
921924 // will try further relaxation, but target's may play further tricks.
922- padInstructionEncoding (RF, Asm.getEmitter (), RemainingSize);
925+ if (padInstructionEncoding (RF, Asm.getEmitter (), RemainingSize))
926+ Sec.setHasLayout (false );
923927
924928 // If we have an instruction which hasn't been fully relaxed, we can't
925929 // skip past it and insert bytes before it. Changing its starting
@@ -936,6 +940,14 @@ bool X86AsmBackend::finishLayout(const MCAssembler &Asm) const {
936940 if (F.getKind () == MCFragment::FT_BoundaryAlign)
937941 cast<MCBoundaryAlignFragment>(F).setSize (RemainingSize);
938942
943+ #ifndef NDEBUG
944+ const uint64_t FinalOffset = Asm.getFragmentOffset (F);
945+ const uint64_t FinalSize = Asm.computeFragmentSize (F);
946+ assert (OrigOffset + OrigSize == FinalOffset + FinalSize &&
947+ " can't move start of next fragment!" );
948+ assert (FinalSize == RemainingSize && " inconsistent size computation?" );
949+ #endif
950+
939951 // If we're looking at a boundary align, make sure we don't try to pad
940952 // its target instructions for some following directive. Doing so would
941953 // break the alignment of the current boundary align.
@@ -949,7 +961,11 @@ bool X86AsmBackend::finishLayout(const MCAssembler &Asm) const {
949961 }
950962 }
951963
952- return true ;
964+ // The layout is done. Mark every fragment as valid.
965+ for (MCSection &Section : Asm) {
966+ Asm.getFragmentOffset (*Section.curFragList ()->Tail );
967+ Asm.computeFragmentSize (*Section.curFragList ()->Tail );
968+ }
953969}
954970
955971unsigned X86AsmBackend::getMaximumNopSize (const MCSubtargetInfo &STI) const {
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