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phoebewangphoebewang
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[X86][AMX-AVX512][NFC] Remove P from intrinsic and instruction name (#123270)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
1 parent baa5b76 commit 48803bc

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16 files changed

+177
-177
lines changed

16 files changed

+177
-177
lines changed

‎clang/include/clang/Basic/BuiltinsX86_64.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -295,8 +295,8 @@ let Features = "amx-complex,amx-transpose", Attributes = [NoThrow] in {
295295

296296
let Features = "amx-avx512,avx10.2-512", Attributes = [NoThrow] in {
297297
def tcvtrowd2ps_internal : X86Builtin<"_Vector<16, float>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
298-
def tcvtrowps2pbf16h_internal : X86Builtin<"_Vector<32, __bf16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
299-
def tcvtrowps2pbf16l_internal : X86Builtin<"_Vector<32, __bf16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
298+
def tcvtrowps2bf16h_internal : X86Builtin<"_Vector<32, __bf16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
299+
def tcvtrowps2bf16l_internal : X86Builtin<"_Vector<32, __bf16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
300300
def tcvtrowps2phh_internal : X86Builtin<"_Vector<32, _Float16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
301301
def tcvtrowps2phl_internal : X86Builtin<"_Vector<32, _Float16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
302302
def tilemovrow_internal : X86Builtin<"_Vector<16, int>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
@@ -387,8 +387,8 @@ let Features = "amx-complex,amx-transpose", Attributes = [NoThrow] in {
387387

388388
let Features = "amx-avx512,avx10.2-512", Attributes = [NoThrow] in {
389389
def tcvtrowd2ps : X86Builtin<"_Vector<16, float>(_Constant unsigned char, unsigned int)">;
390-
def tcvtrowps2pbf16h : X86Builtin<"_Vector<32, __bf16>(_Constant unsigned char, unsigned int)">;
391-
def tcvtrowps2pbf16l : X86Builtin<"_Vector<32, __bf16>(_Constant unsigned char, unsigned int)">;
390+
def tcvtrowps2bf16h : X86Builtin<"_Vector<32, __bf16>(_Constant unsigned char, unsigned int)">;
391+
def tcvtrowps2bf16l : X86Builtin<"_Vector<32, __bf16>(_Constant unsigned char, unsigned int)">;
392392
def tcvtrowps2phh : X86Builtin<"_Vector<32, _Float16>(_Constant unsigned char, unsigned int)">;
393393
def tcvtrowps2phl : X86Builtin<"_Vector<32, _Float16>(_Constant unsigned char, unsigned int)">;
394394
def tilemovrow : X86Builtin<"_Vector<16, int>(_Constant unsigned char, unsigned int)">;

‎clang/lib/Headers/amxavx512intrin.h‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@
6060
/// \headerfile <x86intrin.h>
6161
///
6262
/// \code
63-
/// __m512i _tile_cvtrowps2pbf16h(__tile tsrc, unsigned int row);
63+
/// __m512i _tile_cvtrowps2bf16h(__tile tsrc, unsigned int row);
6464
/// \endcode
6565
///
6666
/// \code{.operation}
@@ -80,14 +80,14 @@
8080
/// zero_tileconfig_start()
8181
/// \endcode
8282
///
83-
/// This intrinsic corresponds to the \c TCVTROWPS2PBF16H instruction.
83+
/// This intrinsic corresponds to the \c TCVTROWPS2BF16H instruction.
8484
///
8585
/// \param tsrc
8686
/// The source tile. Max size is 1024 Bytes.
8787
/// \param row
8888
/// The the row of the source tile.
89-
#define _tile_cvtrowps2pbf16h(tsrc, row) \
90-
__builtin_ia32_tcvtrowps2pbf16h(tsrc, row)
89+
#define _tile_cvtrowps2bf16h(tsrc, row) \
90+
__builtin_ia32_tcvtrowps2bf16h(tsrc, row)
9191

9292
/// Moves a row from a tile register to a zmm destination register, converting
9393
/// the fp32 source elements to bf16. It places the resulting bf16 elements
@@ -97,7 +97,7 @@
9797
/// \headerfile <x86intrin.h>
9898
///
9999
/// \code
100-
/// __m512i _tile_cvtrowps2pbf16l(__tile tsrc, unsigned int row);
100+
/// __m512i _tile_cvtrowps2bf16l(__tile tsrc, unsigned int row);
101101
/// \endcode
102102
///
103103
/// \code{.operation}
@@ -117,14 +117,14 @@
117117
/// zero_tileconfig_start()
118118
/// \endcode
119119
///
120-
/// This intrinsic corresponds to the \c TCVTROWPS2PBF16L instruction.
120+
/// This intrinsic corresponds to the \c TCVTROWPS2BF16L instruction.
121121
///
122122
/// \param tsrc
123123
/// The source tile. Max size is 1024 Bytes.
124124
/// \param row
125125
/// The the row of the source tile.
126-
#define _tile_cvtrowps2pbf16l(tsrc, row) \
127-
__builtin_ia32_tcvtrowps2pbf16l(tsrc, row)
126+
#define _tile_cvtrowps2bf16l(tsrc, row) \
127+
__builtin_ia32_tcvtrowps2bf16l(tsrc, row)
128128

129129
/// Moves a row from a tile register to a zmm destination register, converting
130130
/// the fp32 source elements to fp16. It places the resulting fp16 elements
@@ -238,15 +238,15 @@ static __inline__ __m512 __DEFAULT_FN_ATTRS_AVX512 _tile_cvtrowd2ps_internal(
238238
}
239239

240240
static __inline__ __m512bh __DEFAULT_FN_ATTRS_AVX512
241-
_tile_cvtrowps2pbf16h_internal(unsigned short m, unsigned short n,
242-
_tile1024i src, unsigned u) {
243-
return __builtin_ia32_tcvtrowps2pbf16h_internal(m, n, src, u);
241+
_tile_cvtrowps2bf16h_internal(unsigned short m, unsigned short n,
242+
_tile1024i src, unsigned u) {
243+
return __builtin_ia32_tcvtrowps2bf16h_internal(m, n, src, u);
244244
}
245245

246246
static __inline__ __m512bh __DEFAULT_FN_ATTRS_AVX512
247-
_tile_cvtrowps2pbf16l_internal(unsigned short m, unsigned short n,
248-
_tile1024i src, unsigned u) {
249-
return __builtin_ia32_tcvtrowps2pbf16l_internal(m, n, src, u);
247+
_tile_cvtrowps2bf16l_internal(unsigned short m, unsigned short n,
248+
_tile1024i src, unsigned u) {
249+
return __builtin_ia32_tcvtrowps2bf16l_internal(m, n, src, u);
250250
}
251251

252252
static __inline__ __m512h __DEFAULT_FN_ATTRS_AVX512 _tile_cvtrowps2phh_internal(
@@ -290,7 +290,7 @@ static __m512 __tile_cvtrowd2ps(__tile1024i src0, unsigned src1) {
290290
///
291291
/// \headerfile <immintrin.h>
292292
///
293-
/// This intrinsic corresponds to the <c> TCVTROWPS2PBF16H </c> instruction.
293+
/// This intrinsic corresponds to the <c> TCVTROWPS2BF16H </c> instruction.
294294
///
295295
/// \param src0
296296
/// The 1st source tile. Max size is 1024 Bytes.
@@ -299,8 +299,8 @@ static __m512 __tile_cvtrowd2ps(__tile1024i src0, unsigned src1) {
299299
/// \returns
300300
/// The destination v32bf16 data. Size is 64 Bytes.
301301
__DEFAULT_FN_ATTRS_AVX512
302-
static __m512bh __tile_cvtrowps2pbf16h(__tile1024i src0, unsigned src1) {
303-
return _tile_cvtrowps2pbf16h_internal(src0.row, src0.col, src0.tile, src1);
302+
static __m512bh __tile_cvtrowps2bf16h(__tile1024i src0, unsigned src1) {
303+
return _tile_cvtrowps2bf16h_internal(src0.row, src0.col, src0.tile, src1);
304304
}
305305

306306
/// Move a row from a tile (src0) to a v32bf16 dst, converting the fp32 source
@@ -309,7 +309,7 @@ static __m512bh __tile_cvtrowps2pbf16h(__tile1024i src0, unsigned src1) {
309309
///
310310
/// \headerfile <immintrin.h>
311311
///
312-
/// This intrinsic corresponds to the <c> TCVTROWPS2PBF16L </c> instruction.
312+
/// This intrinsic corresponds to the <c> TCVTROWPS2BF16L </c> instruction.
313313
///
314314
/// \param src0
315315
/// The 1st source tile. Max size is 1024 Bytes.
@@ -318,8 +318,8 @@ static __m512bh __tile_cvtrowps2pbf16h(__tile1024i src0, unsigned src1) {
318318
/// \returns
319319
/// The destination v32bf16 data. Size is 64 Bytes.
320320
__DEFAULT_FN_ATTRS_AVX512
321-
static __m512bh __tile_cvtrowps2pbf16l(__tile1024i src0, unsigned src1) {
322-
return _tile_cvtrowps2pbf16l_internal(src0.row, src0.col, src0.tile, src1);
321+
static __m512bh __tile_cvtrowps2bf16l(__tile1024i src0, unsigned src1) {
322+
return _tile_cvtrowps2bf16l_internal(src0.row, src0.col, src0.tile, src1);
323323
}
324324

325325
/// Move a row from a tile (src0) to a v32fp16 dst, converting the fp32 source

‎clang/lib/Sema/SemaX86.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -641,8 +641,8 @@ bool SemaX86::CheckBuiltinTileArguments(unsigned BuiltinID, CallExpr *TheCall) {
641641
case X86::BI__builtin_ia32_t2rpntlvwz1rs:
642642
case X86::BI__builtin_ia32_t2rpntlvwz1rst1:
643643
case X86::BI__builtin_ia32_t2rpntlvwz0rs:
644-
case X86::BI__builtin_ia32_tcvtrowps2pbf16h:
645-
case X86::BI__builtin_ia32_tcvtrowps2pbf16l:
644+
case X86::BI__builtin_ia32_tcvtrowps2bf16h:
645+
case X86::BI__builtin_ia32_tcvtrowps2bf16l:
646646
case X86::BI__builtin_ia32_tcvtrowps2phh:
647647
case X86::BI__builtin_ia32_tcvtrowps2phl:
648648
case X86::BI__builtin_ia32_tcvtrowd2ps:

‎clang/test/CodeGen/X86/amx_avx512_api.c‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -16,18 +16,18 @@ __m512 test_tile_cvtrowd2ps(__tile1024i a, unsigned b) {
1616
return __tile_cvtrowd2ps(a, b);
1717
}
1818

19-
__m512bh test_tile_cvtrowps2pbf16h(__tile1024i a, unsigned b) {
20-
//CHECK-LABEL: @test_tile_cvtrowps2pbf16h
19+
__m512bh test_tile_cvtrowps2bf16h(__tile1024i a, unsigned b) {
20+
//CHECK-LABEL: @test_tile_cvtrowps2bf16h
2121
//CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
22-
//CHECK-DAG: call <32 x bfloat> @llvm.x86.tcvtrowps2pbf16h.internal
23-
return __tile_cvtrowps2pbf16h(a, b);
22+
//CHECK-DAG: call <32 x bfloat> @llvm.x86.tcvtrowps2bf16h.internal
23+
return __tile_cvtrowps2bf16h(a, b);
2424
}
2525

26-
__m512bh test_tile_cvtrowps2pbf16l(__tile1024i a, unsigned b) {
27-
//CHECK-LABEL: @test_tile_cvtrowps2pbf16l
26+
__m512bh test_tile_cvtrowps2bf16l(__tile1024i a, unsigned b) {
27+
//CHECK-LABEL: @test_tile_cvtrowps2bf16l
2828
//CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
29-
//CHECK-DAG: call <32 x bfloat> @llvm.x86.tcvtrowps2pbf16l.internal
30-
return __tile_cvtrowps2pbf16l(a, b);
29+
//CHECK-DAG: call <32 x bfloat> @llvm.x86.tcvtrowps2bf16l.internal
30+
return __tile_cvtrowps2bf16l(a, b);
3131
}
3232

3333
__m512h test_tile_cvtrowps2phh(__tile1024i a, unsigned b) {

‎clang/test/CodeGen/X86/amxavx512-builtins.c‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -10,16 +10,16 @@ __m512 test_tile_cvtrowd2ps(unsigned int A) {
1010
return _tile_cvtrowd2ps(1, A);
1111
}
1212

13-
__m512bh test_tile_cvtrowps2pbf16h(unsigned int A) {
14-
// CHECK-LABEL: @test_tile_cvtrowps2pbf16h(
15-
// CHECK: call <32 x bfloat> @llvm.x86.tcvtrowps2pbf16h(i8 1, i32 %{{.*}})
16-
return _tile_cvtrowps2pbf16h(1, A);
13+
__m512bh test_tile_cvtrowps2bf16h(unsigned int A) {
14+
// CHECK-LABEL: @test_tile_cvtrowps2bf16h(
15+
// CHECK: call <32 x bfloat> @llvm.x86.tcvtrowps2bf16h(i8 1, i32 %{{.*}})
16+
return _tile_cvtrowps2bf16h(1, A);
1717
}
1818

19-
__m512bh test_tile_cvtrowps2pbf16l(unsigned int A) {
20-
// CHECK-LABEL: @test_tile_cvtrowps2pbf16l(
21-
// CHECK: call <32 x bfloat> @llvm.x86.tcvtrowps2pbf16l(i8 1, i32 %{{.*}})
22-
return _tile_cvtrowps2pbf16l(1, A);
19+
__m512bh test_tile_cvtrowps2bf16l(unsigned int A) {
20+
// CHECK-LABEL: @test_tile_cvtrowps2bf16l(
21+
// CHECK: call <32 x bfloat> @llvm.x86.tcvtrowps2bf16l(i8 1, i32 %{{.*}})
22+
return _tile_cvtrowps2bf16l(1, A);
2323
}
2424

2525
__m512h test_tile_cvtrowps2phh(unsigned int A) {

‎llvm/include/llvm/IR/IntrinsicsX86.td‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -5999,10 +5999,10 @@ let TargetPrefix = "x86" in {
59995999
def int_x86_tcvtrowd2ps : ClangBuiltin<"__builtin_ia32_tcvtrowd2ps">,
60006000
Intrinsic<[llvm_v16f32_ty], [llvm_i8_ty, llvm_i32_ty],
60016001
[ImmArg<ArgIndex<0>>]>;
6002-
def int_x86_tcvtrowps2pbf16h : ClangBuiltin<"__builtin_ia32_tcvtrowps2pbf16h">,
6002+
def int_x86_tcvtrowps2bf16h : ClangBuiltin<"__builtin_ia32_tcvtrowps2bf16h">,
60036003
Intrinsic<[llvm_v32bf16_ty], [llvm_i8_ty, llvm_i32_ty],
60046004
[ImmArg<ArgIndex<0>>]>;
6005-
def int_x86_tcvtrowps2pbf16l : ClangBuiltin<"__builtin_ia32_tcvtrowps2pbf16l">,
6005+
def int_x86_tcvtrowps2bf16l : ClangBuiltin<"__builtin_ia32_tcvtrowps2bf16l">,
60066006
Intrinsic<[llvm_v32bf16_ty], [llvm_i8_ty, llvm_i32_ty],
60076007
[ImmArg<ArgIndex<0>>]>;
60086008
def int_x86_tcvtrowps2phh : ClangBuiltin<"__builtin_ia32_tcvtrowps2phh">,
@@ -6181,13 +6181,13 @@ let TargetPrefix = "x86" in {
61816181
Intrinsic<[llvm_v16f32_ty],
61826182
[llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty, llvm_i32_ty],
61836183
[]>;
6184-
def int_x86_tcvtrowps2pbf16h_internal :
6185-
ClangBuiltin<"__builtin_ia32_tcvtrowps2pbf16h_internal">,
6184+
def int_x86_tcvtrowps2bf16h_internal :
6185+
ClangBuiltin<"__builtin_ia32_tcvtrowps2bf16h_internal">,
61866186
Intrinsic<[llvm_v32bf16_ty],
61876187
[llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty, llvm_i32_ty],
61886188
[]>;
6189-
def int_x86_tcvtrowps2pbf16l_internal :
6190-
ClangBuiltin<"__builtin_ia32_tcvtrowps2pbf16l_internal">,
6189+
def int_x86_tcvtrowps2bf16l_internal :
6190+
ClangBuiltin<"__builtin_ia32_tcvtrowps2bf16l_internal">,
61916191
Intrinsic<[llvm_v32bf16_ty],
61926192
[llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty, llvm_i32_ty],
61936193
[]>;
@@ -7893,4 +7893,4 @@ def int_x86_movrsdi : ClangBuiltin<"__builtin_ia32_movrsdi">,
78937893
[IntrReadMem]>;
78947894
def int_x86_prefetchrs : ClangBuiltin<"__builtin_ia32_prefetchrs">,
78957895
Intrinsic<[], [llvm_ptr_ty], []>;
7896-
}
7896+
}

‎llvm/lib/Target/X86/X86ExpandPseudo.cpp‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -563,10 +563,10 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
563563
case X86::PTILELOADDRST1V:
564564
case X86::PTCVTROWD2PSrreV:
565565
case X86::PTCVTROWD2PSrriV:
566-
case X86::PTCVTROWPS2PBF16HrreV:
567-
case X86::PTCVTROWPS2PBF16HrriV:
568-
case X86::PTCVTROWPS2PBF16LrreV:
569-
case X86::PTCVTROWPS2PBF16LrriV:
566+
case X86::PTCVTROWPS2BF16HrreV:
567+
case X86::PTCVTROWPS2BF16HrriV:
568+
case X86::PTCVTROWPS2BF16LrreV:
569+
case X86::PTCVTROWPS2BF16LrriV:
570570
case X86::PTCVTROWPS2PHHrreV:
571571
case X86::PTCVTROWPS2PHHrriV:
572572
case X86::PTCVTROWPS2PHLrreV:
@@ -595,17 +595,17 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
595595
case X86::PTCVTROWD2PSrriV:
596596
Opc = X86::TCVTROWD2PSrri;
597597
break;
598-
case X86::PTCVTROWPS2PBF16HrreV:
599-
Opc = X86::TCVTROWPS2PBF16Hrre;
598+
case X86::PTCVTROWPS2BF16HrreV:
599+
Opc = X86::TCVTROWPS2BF16Hrre;
600600
break;
601-
case X86::PTCVTROWPS2PBF16HrriV:
602-
Opc = X86::TCVTROWPS2PBF16Hrri;
601+
case X86::PTCVTROWPS2BF16HrriV:
602+
Opc = X86::TCVTROWPS2BF16Hrri;
603603
break;
604-
case X86::PTCVTROWPS2PBF16LrreV:
605-
Opc = X86::TCVTROWPS2PBF16Lrre;
604+
case X86::PTCVTROWPS2BF16LrreV:
605+
Opc = X86::TCVTROWPS2BF16Lrre;
606606
break;
607-
case X86::PTCVTROWPS2PBF16LrriV:
608-
Opc = X86::TCVTROWPS2PBF16Lrri;
607+
case X86::PTCVTROWPS2BF16LrriV:
608+
Opc = X86::TCVTROWPS2BF16Lrri;
609609
break;
610610
case X86::PTCVTROWPS2PHHrreV:
611611
Opc = X86::TCVTROWPS2PHHrre;

‎llvm/lib/Target/X86/X86ISelLowering.cpp‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -37892,8 +37892,8 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3789237892
MI.eraseFromParent(); // The pseudo is gone now.
3789337893
return BB;
3789437894
}
37895-
case X86::PTCVTROWPS2PBF16Hrri:
37896-
case X86::PTCVTROWPS2PBF16Lrri:
37895+
case X86::PTCVTROWPS2BF16Hrri:
37896+
case X86::PTCVTROWPS2BF16Lrri:
3789737897
case X86::PTCVTROWPS2PHHrri:
3789837898
case X86::PTCVTROWPS2PHLrri:
3789937899
case X86::PTCVTROWD2PSrri:
@@ -37906,14 +37906,14 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3790637906
case X86::PTCVTROWD2PSrri:
3790737907
Opc = X86::TCVTROWD2PSrri;
3790837908
break;
37909-
case X86::PTCVTROWPS2PBF16Hrri:
37910-
Opc = X86::TCVTROWPS2PBF16Hrri;
37909+
case X86::PTCVTROWPS2BF16Hrri:
37910+
Opc = X86::TCVTROWPS2BF16Hrri;
3791137911
break;
3791237912
case X86::PTCVTROWPS2PHHrri:
3791337913
Opc = X86::TCVTROWPS2PHHrri;
3791437914
break;
37915-
case X86::PTCVTROWPS2PBF16Lrri:
37916-
Opc = X86::TCVTROWPS2PBF16Lrri;
37915+
case X86::PTCVTROWPS2BF16Lrri:
37916+
Opc = X86::TCVTROWPS2BF16Lrri;
3791737917
break;
3791837918
case X86::PTCVTROWPS2PHLrri:
3791937919
Opc = X86::TCVTROWPS2PHLrri;
@@ -37930,8 +37930,8 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3793037930
MI.eraseFromParent(); // The pseudo is gone now.
3793137931
return BB;
3793237932
}
37933-
case X86::PTCVTROWPS2PBF16Hrre:
37934-
case X86::PTCVTROWPS2PBF16Lrre:
37933+
case X86::PTCVTROWPS2BF16Hrre:
37934+
case X86::PTCVTROWPS2BF16Lrre:
3793537935
case X86::PTCVTROWPS2PHHrre:
3793637936
case X86::PTCVTROWPS2PHLrre:
3793737937
case X86::PTCVTROWD2PSrre:
@@ -37944,11 +37944,11 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3794437944
case X86::PTCVTROWD2PSrre:
3794537945
Opc = X86::TCVTROWD2PSrre;
3794637946
break;
37947-
case X86::PTCVTROWPS2PBF16Hrre:
37948-
Opc = X86::TCVTROWPS2PBF16Hrre;
37947+
case X86::PTCVTROWPS2BF16Hrre:
37948+
Opc = X86::TCVTROWPS2BF16Hrre;
3794937949
break;
37950-
case X86::PTCVTROWPS2PBF16Lrre:
37951-
Opc = X86::TCVTROWPS2PBF16Lrre;
37950+
case X86::PTCVTROWPS2BF16Lrre:
37951+
Opc = X86::TCVTROWPS2BF16Lrre;
3795237952
break;
3795337953
case X86::PTCVTROWPS2PHHrre:
3795437954
Opc = X86::TCVTROWPS2PHHrre;

‎llvm/lib/Target/X86/X86InstrAMX.td‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -585,26 +585,26 @@ let Predicates = [HasAMXAVX512, HasAVX10_2_512, In64BitMode] in {
585585
[(set VR512: $dst,
586586
(int_x86_tcvtrowd2ps_internal GR16:$src1, GR16:$src2,
587587
TILE:$src3, GR32:$src4))]>;
588-
def PTCVTROWPS2PBF16HrriV : PseudoI<(outs VR512:$dst),
589-
(ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
590-
[(set VR512: $dst,
591-
(int_x86_tcvtrowps2pbf16h_internal GR16:$src1, GR16:$src2,
592-
TILE:$src3, imm:$src4))]>;
593-
def PTCVTROWPS2PBF16HrreV : PseudoI<(outs VR512:$dst),
594-
(ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
595-
[(set VR512: $dst,
596-
(int_x86_tcvtrowps2pbf16h_internal GR16:$src1, GR16:$src2,
597-
TILE:$src3, GR32:$src4))]>;
598-
def PTCVTROWPS2PBF16LrriV : PseudoI<(outs VR512:$dst),
599-
(ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
600-
[(set VR512: $dst,
601-
(int_x86_tcvtrowps2pbf16l_internal GR16:$src1, GR16:$src2,
602-
TILE:$src3, imm:$src4))]>;
603-
def PTCVTROWPS2PBF16LrreV : PseudoI<(outs VR512:$dst),
604-
(ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
605-
[(set VR512: $dst,
606-
(int_x86_tcvtrowps2pbf16l_internal GR16:$src1, GR16:$src2,
607-
TILE:$src3, GR32:$src4))]>;
588+
def PTCVTROWPS2BF16HrriV : PseudoI<(outs VR512:$dst),
589+
(ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
590+
[(set VR512: $dst,
591+
(int_x86_tcvtrowps2bf16h_internal GR16:$src1, GR16:$src2,
592+
TILE:$src3, imm:$src4))]>;
593+
def PTCVTROWPS2BF16HrreV : PseudoI<(outs VR512:$dst),
594+
(ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
595+
[(set VR512: $dst,
596+
(int_x86_tcvtrowps2bf16h_internal GR16:$src1, GR16:$src2,
597+
TILE:$src3, GR32:$src4))]>;
598+
def PTCVTROWPS2BF16LrriV : PseudoI<(outs VR512:$dst),
599+
(ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
600+
[(set VR512: $dst,
601+
(int_x86_tcvtrowps2bf16l_internal GR16:$src1, GR16:$src2,
602+
TILE:$src3, imm:$src4))]>;
603+
def PTCVTROWPS2BF16LrreV : PseudoI<(outs VR512:$dst),
604+
(ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
605+
[(set VR512: $dst,
606+
(int_x86_tcvtrowps2bf16l_internal GR16:$src1, GR16:$src2,
607+
TILE:$src3, GR32:$src4))]>;
608608
def PTCVTROWPS2PHHrriV : PseudoI<(outs VR512:$dst),
609609
(ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
610610
[(set VR512: $dst,
@@ -654,8 +654,8 @@ multiclass AMXAVX512_BASE<bits<8> Opcode1, bits<8> Opcode2, string Opstr,
654654

655655
defm TCVTROWPS2PHH : AMXAVX512_BASE<0x6d, 0x07, "tcvtrowps2phh", PS, PS>;
656656
defm TCVTROWPS2PHL : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2phl", PD, XD>;
657-
defm TCVTROWPS2PBF16H : AMXAVX512_BASE<0x6d, 0x07, "tcvtrowps2pbf16h", XD, XD>;
658-
defm TCVTROWPS2PBF16L : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2pbf16l", XS, XS>;
657+
defm TCVTROWPS2BF16H : AMXAVX512_BASE<0x6d, 0x07, "tcvtrowps2bf16h", XD, XD>;
658+
defm TCVTROWPS2BF16L : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2bf16l", XS, XS>;
659659

660660
multiclass m_tilemovrow {
661661
let Predicates = [HasAMXAVX512, HasAVX10_2_512, In64BitMode] in {

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